1. doc.: IEEE 802.15-<doc#>
<month year>
doc.: IEEE <doc#>
September 2004
doc.: IEEE a
Project: IEEE P Working Group for Wireless Personal Area Networks (WPANS)
Submission Title: [Implementation of High Speed FFT processor for MB-OFDM System]
Date Submitted: [September 2004]
Revised: []
Source: [Sang-sung Choi, Sang-in Cho]
Company [Electronics and Telecommunications Research Institute]
Address [161 Gajeong-dong, Yuseong-gu, Daejeon, Korea]
Voice : [ ], FAX : [ ],
Re: [Technical contribution]
Abstract: [This presentation presents the implementation method of IFFT/FFT processor for MB-OFDM UWB system]
Purpose: [Technical contribution to implement IFFT/FFT processor proposed for MB-OFDM UWB system]
Notice: This document has been prepared to assist the IEEE P It is offered as a basis for discussion and is not binding on the contributing individual or organization. The material in this document is subject to change in form and content after further study. The contributor reserves the right to add, amend or withdraw material contained herein.
Release: The contributor acknowledges and accepts that this contribution becomes the property of IEEE and may be made publicly available by P
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2. Implementation of High Speed FFT processor for MB-OFDM System
September 2004
Implementation of High Speed FFT processor for MB-OFDM System
Sang-Sung Choi
Sang-In Cho
ETRI

3. September 2004
Introduction
MB-OFDM UWB proposal requires high speed IFFT/FFT processors with 128-point computation.
Digital signals processed in IFFT processor change into analog signals by DAC, and then pass through the sharp LPF to satisfy the transmitting PSD mask.
- Transmitter using 128-point IFFT processor (DAC speed : 528MHz)
- LPF shape & Frequency spectrum of OFDM signal after DAC
ETRI

4. September 2004
Introduction
The TX LPF is very important to determine the transmit PSD mask
of MB-OFDM UWB system, but the TX LPF design is not easy to
satisfy the Transmit PSD mask of MB-OFDM.
Two methods are considered to design the TX LPF satisfying the
transmit PSD mask.
1) fix 528MHz sampling rate of DAC , and design high order TX LPF
2) increase sampling rate of DAC, and reduce the order of TX LPF
Use 2 times over-sample rate at DAC to design the TX LPF.
- Reduce the order of TX LPF
- It has advantage of the performance compared to method 1).
 Presented by DOC IEEE /275r0
There are trade-offs between two methods for considering power
consumption and gate size etc.
 ETRI is developing a prototype UWB system using 256-point IFFT
processor (DAC speed : 1056MHz)
ETRI

5. Proposed IFFT Processor Approach
September 2004
Proposed IFFT Processor Approach
For easy low pass filtering of 528MHz baseband signal after DAC, we have to make space between OFDM signals that are repeated in frequency spectrum, which is accomplished by 128-point zero-padding.
- Transmitter using 256-point IFFT processor (DAC speed : 1056MHz)
- LPF shape & Frequency spectrum of OFDM signal after DAC
ETRI

6. IFFT/FFT Processor Specification
September 2004
IFFT/FFT Processor Specification
Input data of FFT processor are QPSK modulated 128-point complex data
Input data of IFFT processor become 256-point that consisted of QPSK modulated 128-point complex data and 128-point zeros.
- Input data of original IFFT processor (128-point QPSK data)
- Input data of proposed IFFT processor (128-point QPSK data point zeros)
ETRI

7. Proposed transceiver for MB-OFDM UWB PHY proposal
September 2004
Proposed transceiver for MB-OFDM UWB PHY proposal
Input : 4 samples/clock
Output : 8 samples/clock
Output : 4 samples/clock
ETRI

8. Characteristics of Multipliers
September 2004
Characteristics of Multipliers
Multiplier is one of the most dominant elements
in FFT/IFFT implementation
Standard 2’s Complement Multiplier
(W-bit) x (W-bit) = (2W-1)-bit
Many DSP applications need only W-bit products
Fixed-Width Multiplier
Quantization to W-bit by eliminating (W-1) Least Significant Bits
Can reduce area by approximately 50% but Truncation Error is introduced
Proper Error Compensation Bias needed
Canonic Signed Digit Multiplier
Constant coefficient
33% fewer nonzero digits than 2’s complement numbers
Modified Booth Multiplier
Variable coefficient
The number of partial products has been reduced to W/2
These multipliers can achieve about 40% reduction in area and power consumption
ETRI

9. The radix-24 structure of FFT processor
September 2004
The radix-24 structure of FFT processor
DFT :
Radix-2 structure
Radix-24 structure
CSD multiplier
CSD multiplier
Modified Booth multiplier
ETRI

10. The structure of 256-point IFFT processor
September 2004
The structure of 256-point IFFT processor
32-point Radix-24 FFT structure
8-level parallelism
DIF (Decimation In Frequency), SDF (Single Delay Feedback)
Fixed CSD & Modified Booth multipliers used
ETRI

11. The structure of 256-point IFFT processor
September 2004
The structure of 256-point IFFT processor
Butterfly unit : 48
-j multiplier : 22
CSD multiplier : 16
Modified Booth Multiplier : 8
ETRI

12. The structure of 256-point IFFT processor
September 2004
The structure of 256-point IFFT processor
CSD multiplier
Modified Booth multiplier
CSD multiplier
ETRI

13. The structure of 128-point FFT processor
September 2004
The structure of 128-point FFT processor
32-point Radix-24 FFT structure
4-level parallelism
DIF (Decimation In Frequency), SDF (Single Delay Feedback)
Fixed CSD & Modified Booth multipliers used
ETRI

14. The structure of 128-point FFT processor
September 2004
The structure of 128-point FFT processor
CSD multiplier
Modified Booth multiplier
CSD multiplier
Butterfly unit : 24
-j multiplier : 11
CSD multiplier : 8
Modified Booth Multiplier : 4
ETRI

15. Simulation result of 256-point IFFT processor
September 2004
Simulation result of 256-point IFFT processor
Constellation
Input Bit resolution : 3
Output bit resolution : 20
Multiplier coefficient bit : 10
SQNR : 52dB
Input Bit resolution : 3
Output bit resolution : 11
Multiplier coefficient bit : 8
SQNR : 30dB
ETRI

16. Simulation result of 128-point FFT processor
September 2004
Simulation result of 128-point FFT processor
Constellation
Input Bit resolution : 10
Output bit resolution : 20
Multiplier coefficient bit : 10
SQNR : 52dB
Input Bit resolution : 10
Output bit resolution : 12
Multiplier coefficient bit : 8
SQNR : 30dB
ETRI

17. Summary of simulations
September 2004
Summary of simulations
IFFT processor
Points
Parallel level
SQNR (dB)
Gate Count
256 8 52
about 100k 30
about 80k
FFT processor
Points
Parallel level
SQNR (dB)
Gate Count
128 4 52
about 50k 30
about 40k
ETRI

18. Conclusion 256-point IFFT processing for easy Low Pass Filtering
September 2004
Conclusion
256-point IFFT processing for easy Low Pass Filtering
Parallel structure for high speed signal processing
IFFT/FFT processor
32-point radix-24 DIF SDF structure
Small area, low power, high speed operation
Canonic Signed Digit Multiplier – constant coefficients
Modified Booth Multiplier – variable coefficients
IFFT processor
FFT processor
Point
256-point
128-point
Parallelism 8 4
Number of input data (sample/clock)
Throughput (sample/clock)
Latency (except S/P, reverse unit) 32
Number of gates (30dB SQNR)
About 80K
About 40K
ETRI