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1HSSPG Georgia Tech High Speed Image Acquisition System for Focal-Plane-Arrays Doctoral Dissertation Presentation by Youngjoong Joo School of Electrical and Computer Engineering Georgia Institute of Technology February 12, 1999
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2HSSPG Georgia Tech Outlines u Introduction u Background u Readout system architectures u Compact ovrsampling conversion u Photodetectors u Test u Conclusion and future work
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3HSSPG Georgia Tech Introduction u Motivation Conventional focal-plane-arrays (FPAs) readout methods are not suitable for some scientific and engineering applications. 3Low readout speed 1MHz 1000X1000 14 bit images 62THz 3Not scalable depending on the readout architecture 3Noise sensitive
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4HSSPG Georgia Tech Introduction u Objective Design a new high speed scalable image acquisition system for FPAs. 3High frame rates (> 100kfps) 3Scalable 3Low noise
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5HSSPG Georgia Tech Background A/D Converters A/D Converters Readout Systems Readout Systems Photo detectors DSP u Block diagram
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6HSSPG Georgia Tech Photo detectors u Hybrid integration 3High responsivity 3High fill factor 3Substrate must be transparent 3Higher fabrication cost u Generate electronic signals and are located at the front end of the image acquisition system.
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7HSSPG Georgia Tech Photo detectors u Monomaterial integration 3Compatibility with integration on-chip electronics 3Low cost 3Low absorption coefficient
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8HSSPG Georgia Tech A/D converters u What is important for the focal-plane-applications? Size, robustness, variable resolution u Conventional A/D converters Flash ADC, Successive Approximation ADC Single slope ADC, Cyclic ADC, Oversampling ADC
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9HSSPG Georgia Tech A/D converters *) modulator only
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10HSSPG Georgia Tech Readout systems u Support an optimum interface between the detectors and the following signal processing stage.
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11HSSPG Georgia Tech Readout systems u Serial readout system 3Noise reduction 3Not scalable 3Slow readout speed u Semi-parallel readout system 3Increase the readout speed 3Less sensitive to noise at the analog signal path
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12HSSPG Georgia Tech Readout system architecture u Fully parallel readout system was designed as a scalable FPA readout system
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13HSSPG Georgia Tech Readout system architecture u Signal path from image detector to signal processor 01010 010 Emitter driver Emitter Detector ReceiverComparatorSIMPil processor
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14HSSPG Georgia Tech Readout system architecture u Two layer FPA system photomicrograph
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15HSSPG Georgia Tech Readout system architecture u Readout speed comparison with same ADCs 64
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16HSSPG Georgia Tech Readout system architecture u Readout speed comparison with different ADCs 288 X 288 168MHz15bits 4GHz
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17HSSPG Georgia Tech Compact oversampling conversion u Oversampling ADC Oversampling converters trade speed for accuracy Analog input Noise shaping modulator PCM Oversampling clock f S Decimator and Digital LPF Nyquist clock f N 1-bit stream
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18HSSPG Georgia Tech Compact oversampling conversion u Quantization noise of oversampling modulator Each doubling of the sampling frequency decreases the in- band noise by 3 dB. f0f0 f S /2 PSD Freq. Signal Quantization noise f0f0 f S /2 PSD Freq. Signal In band quantization noise Removed by low pass filtering
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19HSSPG Georgia Tech Compact oversampling conversion u Modulation noise of higher order oversampling modulator Each doubling of the sampling frequency decreases the in- band noise by (3+6n) dB. f0f0 f S /2 PSD Freq. 1 st order quantization noise 2 nd order quantization noise Modulation noise
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20HSSPG Georgia Tech Compact oversampling conversion u Current input oversampling modulator 3Oversampling loop linearity is improved. 3Amplifiers are removed from the feedback. 3Linear D/A conversion is available.
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21HSSPG Georgia Tech Compact oversampling conversion u Current buffer 3Low input impedance 3Stabilize the detector bias voltage
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22HSSPG Georgia Tech Compact oversampling conversion u Current D/A converter u Integrator Metal 3 Metal 2 Metal 1 Current in GND Current in Integrator
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23HSSPG Georgia Tech Compact oversampling conversion u Comparator (G. M. Yin) Sampling rate : 100MHz, Input signal : 0.1V 10MHz Input signal Output signal
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24HSSPG Georgia Tech Compact oversampling conversion u Overall system Current buffer & Photo detector Integrator & Current DAC Integrator Comparator
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25HSSPG Georgia Tech Compact oversampling conversion u Overall system simulation results Integrator output voltage Modulator output Freq. PDF [dB] 50 kHz input signal Modulation noise
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26HSSPG Georgia Tech Compact oversampling conversion u Circuit noise attenuation Delay xixi e di e ci yiyi wiwi + + - where, e di = detector, current buffer, and current D/A converter noise and e ci = quantization and comparator noise.
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27HSSPG Georgia Tech Compact oversampling conversion u Layouts 3To make a large detector, all the effort were applied to design a compact circuit. 3Input parts of the circuits were carefully designed not to overlapped with digital lines. 3To reduce the offset and improve the switching time of the comparator, all the components were carefully layout to make a matched comparator. 3When the capacitor was laid-out, metal 1 and metal 3 layers were connected to the GND to prevent the metal-substrate capacitor. 3The latch transistor size was optimized to drive a high capacitor load which is connected to several pixels through a long data line.
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28HSSPG Georgia Tech Compact oversampling conversion u Photomicrographs Detector Circuits Capacitor Pad Circuits
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29HSSPG Georgia Tech Photodetectors u Hybrid detectors 8X8 detectorstop contact
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30HSSPG Georgia Tech Photodetectors u Monomaterial detectors V bias GND n+n+ n+n+ p+ p n+ p+
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31HSSPG Georgia Tech Photodetectors u Monomaterial detectors 8X8 detectorstest structuresemitter driver
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32HSSPG Georgia Tech Test u Test setup 3Arbitrary waveform generator (AWG2041) 3DC current sources (Keithley SMU 236) 3Sampling oscilloscope (Tektronix 11403A) 3Transient capture oscilloscope (Tektronix 3Multi-function optical meter (Newport 1835-c) 3Digital data acquisition card (CYDIO 192T) 350MHz 486 processor 3233MHz Pentium processor 3Newport coated ND filters
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33HSSPG Georgia Tech Test u Electrical testing –Verify the functionality of the circuit 1.000uA 2.013V Oscilloscope DC current source
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34HSSPG Georgia Tech Test u Electrical testing results Input = 0.03 AInput = 0.06 A
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35HSSPG Georgia Tech Test u Slow speed testing setup 1 1 2 11 8 6 4 1 1 2 5 8 11 11 5 1 1 4 16 10 16 16 16 2 5 4 10 16 16 16 16 1 3 5 16 16 16 16 16 1 3 3 8 16 16 16 10 0 1 2 2 10 16 11 11 1 1 0 2 2 6 4 4 1
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36HSSPG Georgia Tech Test u Slow speed testing : sampling rate=1MHz
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37HSSPG Georgia Tech Test u Uniformity Low light intensityHigh light intensity
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38HSSPG Georgia Tech Test u Linearity 64 pixels data6 bits linearity Saturation 6 bit range
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39HSSPG Georgia Tech Test u Nonlinearity 3The nonlinearity of the small light intensity was not coming from the FPA system but the optical filter. 3The nonlinearity of the high light intensity was coming from the saturation of the system Measured data Test data
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40HSSPG Georgia Tech Test u System noise The system noise is over than 8 bits.
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41HSSPG Georgia Tech u High speed testing To obtain a 8 bit 100kfps image : 3oversampling ratio : 26 3modulator bandwidth : 2.6 MHz 3System bandwidth : 167 MHz Test
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42HSSPG Georgia Tech u Modulator Test 2 MHz4 MHz
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43HSSPG Georgia Tech u Output with 2.5MHz system frequency. Test Microscope lightRoom light
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44HSSPG Georgia Tech u Output with 40MHz system frequency. Test Microscope lightRoom light
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45HSSPG Georgia Tech u Output with 100MHz system frequency. Test Microscope lightRoom light
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46HSSPG Georgia Tech u A new high speed readout system for FPAs were designed and tested. 3A new readout architecture was designed. 3A new current input first-order sigma-delta A/D modulator was designed. 3Two kinds of photo detectors were utilized. 3Several tests had been done to verify the proposed system. Conclusion and future works
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47HSSPG Georgia Tech u To complete the fully parallel readout system for FPAs, two things need to be tested and verified. 3Test the speed of the through-wafer optical communication. 3Test with a microprocessor. 3The focal-plane-array chip and the microprocessor chip need to be stacked and test together. Conclusion and future works
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48HSSPG Georgia Tech Whole system
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