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Analysis of a dip-solder process for self-assembly Madhav Rao (ECE) The University of Alabama Research Professors – Dr. John C Lusth (CS) Dr. Susan L Burkett.

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Presentation on theme: "Analysis of a dip-solder process for self-assembly Madhav Rao (ECE) The University of Alabama Research Professors – Dr. John C Lusth (CS) Dr. Susan L Burkett."— Presentation transcript:

1 Analysis of a dip-solder process for self-assembly Madhav Rao (ECE) The University of Alabama Research Professors – Dr. John C Lusth (CS) Dr. Susan L Burkett (ECE) Madhav Rao October 21 1/27

2 Madhav Rao October 21 Earlier work: Dr. Gracias Research Group Source: Timothy G. Leong,, Paul A. Lester, Travis L. Koh, Emma K. Call, and, David H. Gracias, “Surface Tension-Driven Self-Folding Polyhedra”, Langmuir 2007 23 (17), 8747-8751: Supporting information electronic files, ACS Copyrights. Aqueous HCL solution Self assembled structure Self Assembly movie 2/27

3 Madhav Rao October 21 Source: Timothy G. Leong,, Paul A. Lester, Travis L. Koh, Emma K. Call, and, David H. Gracias, “Surface Tension-Driven Self-Folding Polyhedra”, Langmuir 2007 23 (17), 8747-8751: Supporting information electronic files, ACS Copyrights. Snapshots of the video Free floating 3D structures 3/27

4 Madhav Rao October 21 Earlier work: Our research group Source: M. Rao, J. C. Lusth, S. L. Burkett, “Self-assembly solder process to form three-dimensional structures on silicon”, J. Vac. Sci. Technol. B, Vol. 27, No. 1, January 2009. 2D patterns Anchored 3D structures Fig 1: Images showing 3D structures formed from 2D metal patterns 4/27

5 Madhav Rao October 21 Earlier work: Process flow Conventional metal patterning and dip soldering process Fig 2: Process flow diagram. SiO 2 etched window Chromium adhesive layer deposition Gold seed layer deposition Develop Resist Spin Resist 2.5 µm Nickel electroplating 1.5 µm Copper electroplating Resist strip; Seed layer and adhesive layer etching Resist around patterned structures Dip soldering at 65 ºC Resist and sacrificial layer removal Auto folded structures, after solder reflow Source: M. Rao, J. C. Lusth, S. L. Burkett, “Self-assembly solder process to form three-dimensional structures on silicon”, J. Vac. Sci. Technol. B, Vol. 27, No. 1, January 2009. 3-D micro-scale Polyhedron 5/27

6 Madhav Rao October 21 Principle of Surface Tension: Solder Self Assembly Surface tension principles Surface area minimization drives the assembly process. Fig 3: Schematic representation of solder-driven self assembly: before solder reflow. Fig 3: Schematic representation of solder-driven self assembly: after solder reflow. Image redrawn from: K. Harsh, Y.C. Lee, “Modelling for solder self-assembled MEMS, in: Proceedings of the SPIE”, San Jose, CA, 24–30 January 1998, pp. 177–184. 6/27

7 Madhav Rao October 21 Earlier work: Self assembly solder process to form 3D structures Cube Square PyramidTruncated Pyramid Pyramid Truncated Square Pyramid Fig 4: Self Assembled 3D shapes Source: M. Rao, J. C. Lusth, S. L. Burkett, “Self-assembly solder process to form three-dimensional structures on silicon”, J. Vac. Sci. Technol. B, Vol. 27, No. 1, January 2009. 7/27

8 Madhav Rao October 21 Fig 5: Images showing structures: after Ni–Cu electroplating (column 1), after Cr–Au etch (column 2), after solder reflow (column 3), and representative failures (column 4) Source: M. Rao, J. C. Lusth, S. L. Burkett, “Self-assembly solder process to form three-dimensional structures on silicon”, J. Vac. Sci. Technol. B, Vol. 27, No. 1, January 2009. Focusing on failures 8/27

9 Madhav Rao October 21 Maximum yield: 50 % Fig 6: Yield as a function of polyhedron type. Solder Self Assembled Polyhedra Yield 9/27

10 Madhav Rao October 21 Motivation Can we control the solder deposition process and improve the yield ? Thickness Roughness 10/27

11 Madhav Rao October 21 Dip soldering process Dip Temperature Flux Temperature Solder alloys Blanket samples Patterned samples 11/27

12 Madhav Rao October 21 Solder alloys Trade namesStoichiometry M.P. in ⁰ C Internal Designation LMA11744.7Bi-22.6Pb-8.3Sn-5.3Cd-19.1In47SA47 LOW20352.5Bi-32Pb-15.5Sn95SA95 LMA28158Bi-42Sn138SA138 INDALLOY24195.5Sn-3.8Ag-0.7Cu217SA217 Table 1: Different solders used 12/27

13 Madhav Rao October 21 Difference: Heating flux and flux at room temperature for blanket samples Fig 7: Roughness of dip-soldering at low dipping temperatures of SA95 solder alloy 13/27

14 Madhav Rao October 21 Blanket samples: Low Dipping temperature roughness data Fig 8: Roughness of dip-soldering at low dipping temperatures of solder alloys 14/27

15 Madhav Rao October 21 Blanket samples: High Dipping temperature roughness data Fig 9: Roughness of dip-soldering at high dipping temperatures of solder alloys with flux maintained at room temperature 15/27

16 Madhav Rao October 21 Fig 10: Thickness of dip-soldering at low dipping temperatures of solder alloys Blanket samples: Low dipping temperature thickness data 16/27

17 Madhav Rao October 21 Blanket samples: High dipping temperature thickness data Fig 11: Thickness of dip-soldering at high dipping temperatures of solder alloys with flux maintained at room temperature 17/27

18 Madhav Rao October 21 Blanket samples: Experimental analysis Trend of decreased roughness and thickness is observed as dip-temperature increases. Better uniformity at higher temperature is achieved except for SA217 alloy. At the higher dipping temperatures, the highest melting point solder results in a significantly thicker layer than the other solders. Low melting point alloy shows less variation in thickness and roughness. This suggests better uniformity when using low melting-point alloy. Preheating flux improves uniformity for temperatures only near the melting-point of alloy. 18/27

19 Madhav Rao October 21 BarsDividersLinkers Pattern designations 19/27

20 Madhav Rao October 21 Processing Conditions SoldersDip Time Dip Temperature Pattern Names Average Yield in % Standard Error in % SA4790 seconds50 C Bars 89.374.530 Linkers 90.096.787 Dividers 97.160.565 SA952 seconds50 C Bars 98.790.909 Linkers 91.590.476 Dividers 97.160.568 SA1382 seconds40 C Bars 85.953.188 Linkers 89.845.714 Dividers 88.501.000 Dip soldering process for three different solder alloys Table 2: Dip soldering process and yield for copper metal patterns SA95 shows consistent and less varying wetting yield for different patterns 20/27

21 Madhav Rao October 21 Wetting yield: Analysis Blanket samples did not require significant dipping time. We suspect: The lowest melting point alloy needs to overcome the resistance provided by the high density of non-wetting regions around the metal pads. The higher melting point alloy provided the necessary thermal energy to wet the patterns. SA47 required 90 seconds of dip-time for complete coverage. 21/27

22 Madhav Rao October 21 Fig 12: Thickness of pattern dip-soldering Thickness measurement of solder alloys on patterned samples 22/27

23 Madhav Rao October 21 Patterned samples: Experimental analysis Thickness of deposited solder remains low for Bar, as compared to other designs: Linker and Divider. Bar Linker Divider 23/27

24 Madhav Rao October 21 Roughness measurement of solder alloys on patterned samples Fig 13: Roughness of pattern dip-soldering 24/27

25 Madhav Rao October 21 Conclusions Blanket Samples Better uniformity is obtained at higher dip temperatures, especially for the lowest melting-point alloy. Heated flux is preferable for dip- soldering at temperatures near the melting-point of the alloy. Dip solder thickness depends on alloy melting-point. Patterned Samples Coverage of individual elements when dip soldered is pattern dependent. Consistent coverage is obtained using SA95. A change in the dip soldering procedure was needed for patterned samples. 25/27

26 Madhav Rao October 21 Future Work Bridging and folding study on uniform solder deposited patterned samples. Experiments on dipping time over varying density of metal pads. Hollow polyhedra with minimum amount of deposited solder. Two sided 3D VLSI chips [A. Kamto et.al] Can this lead to wireless signal points on a chip ?? Receiving Antenna Transmitting Antenna Fig 14: Wireless signal transmission prototype. Source: A. Kamto, Y. Liu, L. Schaper and S. L. Burkett,, “Reliability study of through-silicon via (TSV) copper filled interconnects”, Thin Solid Films, Vol. 518, No. 5, 2009 26/27

27 Madhav Rao October 21 Acknowledgments College of Engineering, UA CAF facilities, UA. Questions, Comments and Suggestions !! 27/27


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