1. 1 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil The B A B AR Silicon Vertex Tracker Douglas Roberts University of California, Santa Barbara B A B AR Collaboration

2. 2 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Outline n B A B AR and PEP-II Design and Physics Goals n Silicon Vertex Tracker (SVT) Design Considerations n SVT Description –Layout –Silicon Wafers –Upilex Fanouts –Readout Electronics »Front End IC (AToM Chip) »Hybrid and Tails –Mechanical Support n Assembly and Testing n Prelim. Results From Recent System Test and Beam Test n Project Status

3. 3 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil B A B AR SVT Collaborators n Italy –INFN, Ferrara –INFN, Milano –INFN, Pavia –INFN, Pisa –INFN, Torino –INFN, Trieste n U.S.A. –U.C., San Diego –U.C., Santa Barbara –U.C., Santa Cruz –Lawrence Berkeley National Laboratory –Stanford University –U of Wisconsin

4. 4 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil B A B AR Physics Goals n International collaboration of ~530 physicists and engineers from 10 countries n Primary physics goal of the B A B AR experiment is the systematic study of CP asymmetries in the decays of B 0 and B 0 mesons. –Reconstruct one of the B 0 mesons in an exclusive CP-study final state –Tag the flavor of the other B meson in the event –Measure the relative decay time of the two B mesons. e + e -  (4s),  = 0.56 B 0, z CP B 0, z tag

5. 5 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil B A B AR Physics Goals (cont.) n Standard Model predicts a time-dependent CP asymmetry: Time integral of A f (t) = 0 at  (4s), which makes a measurement of the time dependence essential –Reason for asymmetric collider –Good vertex determination extremely important

6. 6 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil PEP-II at SLAC n Asymmetric e + e - collider –E - = 9.000GeV, E + = 3.109GeV L = 3.0 x 10 33 cm -2 s -1, ultimately 10 34. –~30M BB/10 7 s n Time between beam crossings = 4.2ns 0  crossing angle –Final focus dipoles ~20cm from IP –Very little space for SVT readout electronics

7. 7 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil SVT Design Considerations n Vertexing Requirements –Mean vertex separation of 250  m  want single vertex resolution better than ~80  m. –Readily achieved with silicon strip detectors n Acceptance –Want as close to 4  as possible –Magnets at 17.2 , both forward and backward –Boost makes forward region very important »Move most manifolds and flanges to the rear –Coverage from 20  <  < 150 . »In center-of-mass, 0.84 > cos  cm >-0.95 –All electronics outside of active tracking volume n Stand-alone tracking –Drift chamber begins at 22.5cm, so need to reconstruct particles with p t < 100MeV in SVT alone. n Radiation Tolerance –Layer 1 averages ~33 krad/yr »Non-uniform in  »Local max of 240 krad/yr for ~6 

8. 8 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil SVT Layout n 5 Layers of double sided AC coupled silicon microstrip detectors n Inner 3 layers have six modules arranged azimuthally around the beampipe n Outer 2 layers have 16 and 18 modules, respectively.

9. 9 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil SVT Layout (cont.) Each layer has strips oriented parallel (  strips) and perpendicular (z strips) to the beam line n Total of 340 silicon wafers of 6 different types n About 0.94m 2 of silicon n ~150,000 readout channels 350mr30  Kevlar/Carbon Fiber Support Structure Carbon Fiber Support Cone Hybrid Silicon Beam Pipe (~1% X 0 )

10. 10 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil SVT Layout (cont.) End View of BaBar Silicon Vertex Detector

11. 11 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Silicon Wafers n 6 different wafer models n Wafers manufactured by Micron Made of 300  m thick high resistivity silicon with a [111] orientation

12. 12 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Silicon Wafers: Mechanical Specifications n ‘Physical Strip Pitch’ includes floating strip (strips not connected to readout electronics) Models I, II and III have  strips on the  side; Models IV, V and VI have  strips on the J side  strips on wedge detector vary such that the ratio between width and pitch is a constant

13. 13 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Model II Wafer,  -Side (  )

14. 14 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Model II Wafer, J-Side (z)

15. 15 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Model VI Wafer (wedge), J-Side (  )

16. 16 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Summary of Measured Wafer Parameters Quantity R bias V depl I bias C IS C AC C back R s (implant) R s (metal) Radiation Damage Value ~5 M  (varies) 15-40 V <100nA/cm 2 1 pF/cm 20-40 pF/cm * 0.2, 0.4 pF/cm * 27, 55 k  /cm * 7, 13  /cm ~ 300 nA/cm 2 /Mrad * Depends on model number

17. 17 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Upilex Fanouts n Provide an electrical connection between the metal strips on the silicon wafers and the front-end chip n Gang together z strips on outer 2 layers (2 strips read out by same electronics channel) n Testing area allows for testing before readout electronics are attached Layer 2 Fanouts Z Fanout  Fanout Testing Area

18. 18 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Upilex Details 50  m thick Upilex ™ substrate –UBE Industries Ltd, Japan. 4.5  m Cu layer deposited on an adhesive 150nm Cr layer n Cu and Cr are etched to create circuit 150nm of Cr followed by 1  m Au (for wire bonding) are then electrolithically deposited Trace resistance is typ. 2  /cm n Inter-trace capacitance = 0.52pF/cm

19. 19 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Front-end IC (AToM Chip) n Must amplify, shape and digitize input in parallel for all channels n Buffer for duration of Level 1 trigger latency n Sparsify data for readout n High rates and small time between beam crossings (4.2ns) implies data acquisition, digitization, buffering and readout must occur simultaneously

20. 20 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Photo of Rad-Soft AToM  128 channels

21. 21 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Shaper Output n Shaping time set to 100ns (setable to 100, 200, 300 or 400ns) n Charge injected via on-chip calibration circuitry

22. 22 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Time-Over-Threshold Output n Comparison of analog ToT measured at comparator output and digitized ToT

23. 23 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Expected Noise Performance n Based on full SPICE simulation –Front-end circuit –Detector network based on measured detector parameters –Upilex fanout

24. 24 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Test Bench Results Layer 2 Module n Test bench consists of prototype of full SVT readout system: –Silicon + Upilex –Rad-Soft AToM chip and Hybrid –Prototype data transmission and DAQ Decreasing Threshold # Firings/(50 events) Threshold (DAC cnts) Threshold Scan

25. 25 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Test Bench Results Layer 2 Module Measured Offsets and Gains for 2 ICs

26. 26 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Test Bench Results Layer 2 Module Noise (in DAC counts) Measured from Threshold Scan  Side ENC  1070 e - (calc = 880 e - ) J Side ENC  860 e - (calc = 600 e - )

27. 27 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Hybrid n Double sided, multi-layer, thick-film circuit fabricated on 1.2mm thick AlN n 3 Different Models –H1 (Layers 1 and 2) has 7 ICs/side –H2 (Layer 3) has 10 ICs/side –H3 (Layers 4 and 5) has 4 ICs on  side, 5 on z side n Connects to power and data transmission system via flexible multi-layer kapton/copper tail (2 per hybrid)

28. 28 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Hybrid Pictures Component Layout of H1 (Layers 1 and 2) with 7 ICs per side Photograph of H3 prototype (Layers 4 and 5)

29. 29 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Mechanical Support: Ribs and ‘Foot’ Kevlar / Carbon Fiber Support Rib Molded Carbon Fiber Endpieces Layer 2 Rib and Endpiece Assembly Exploded View of ‘Foot’ Region Kevlar/CF Ribs CF Endpiece Cooling Ring Silicon Upilex Fanouts AlN Hybrid AToM IC Berg connector and tails

30. 30 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Mechanical Support 6 Modules mounted on brass cooling rings, which are mounted on carbon fiber support cones 6 Forward and Backward cones held together with carbon fiber space frame 6 Entire assembly mounted on B1 magnets (final focus RE dipoles)

31. 31 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Finished Space Frame

32. 32 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Module Assembly and Testing Layer 2 Half- Module in ‘Ringframe’ fixture. Upilex testing area still attached.  Side z Side

33. 33 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Testing Probe n Automated probe for testing modules before readout IC is attached n Uses 256-pin probe array to contact testing area on Upilex fanout n Connects to pA meter / Voltage source, LCR meter, single channel Q-amp

34. 34 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Attachment of Hybrid n Upilex testing area is removed n Hybrid is attached to Upilex n Still utilizes same ringframe fixture

35. 35 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Module Stiffening Gluing carbon fiber / Kevlar ribs to a Layer 2 Module Finished Module after rib attachment (upside-down)

36. 36 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Arch Module Assembly n Module is assembled flat –Wafer-to-wafer gluing (except at bend) –Upilex fanout glued to silicon –Wirebonding and testing –Attachment to hybrid Bend angles vary from 21  to 28  n Bending operation done on three fixtures that simulate the positions of the support cone mounting buttons –Defines rotation angle and axis n Stiffening ribs attached after bending is complete.

37. 37 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Prelim. Testbeam Results n CERN testbeam run with prototype layer 2 and layer 5 modules n Just finished data taking Monday, Aug. 25 n All results are VERY PRELIMINARY –Chip calibration not done. –No alignment corrections made Correlation between projected track position and hits in the SVT module

38. 38 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Prelim. Testbeam Results Position correlation vs. angle of incident track.

39. 39 The B A B AR Silicon Vertex TrackerDouglas Roberts, UCSB Vertex ‘97, Mangaratiba, Brazil Project Status n Many mechanical parts fabricated: support cones, space frame, ribs, endpieces... n Silicon wafer production underway; all 6 models perform as expected –~60% of wafers already delivered from Micron n System test has verified a working readout system with reasonable noise performance n Final version of AToM IC has been submitted for rad-hard fabrication; expect chips in Dec. n First Layer 2 and Layer 5 modules have been constructed n Goal for installation: End of 1998