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Introduction to Computing Systems from bits & gates to C & beyond Chapter 3 Digital Logic Structures Transistors Logic gates & Boolean logic Combinational.

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Presentation on theme: "Introduction to Computing Systems from bits & gates to C & beyond Chapter 3 Digital Logic Structures Transistors Logic gates & Boolean logic Combinational."— Presentation transcript:

1 Introduction to Computing Systems from bits & gates to C & beyond Chapter 3 Digital Logic Structures Transistors Logic gates & Boolean logic Combinational logic Storage Elements Memory

2 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 2 Transistors An electronic switch  like light switch or faucet  switches between insulator and conductor  switch is closed (conducts) between A & B  depending on the voltage on G (gate) Open switch: no current flows Closed switch: current flows

3 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 3 A B G A B G N Closed if gate is “on” Open if gate is “off” P Open if gate is “on” Closed if gate is “off” A B G CMOS Transistors CMOS  = Complementary Metal-Oxide Semiconductor  Standard type for digital applications  Two types: N (negative) and P (positive)  N and P transistors operate in inverse modes

4 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 4 2.9 v 0 v Out In Inverter Gate  When the input is on (In = high voltage), the P-type transistor is open and the N- type is closed, so the output is off (Out = low voltage).  Vice-versa: when the Input is off (In = low voltage), the output is connected to the high voltage. P N

5 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 5 NOR Gate C A B 2.9 v 0 v P N P N

6 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 6 NOR Gate - Operation 2.9 v 0 v P N P 2.9 v 0 v N P N 2.9 v 0 v N P N P N 2.9 v 0 v P

7 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 7 OR Gate D A B C = a NOR gate followed by an inverter

8 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 8 NAND & AND Gates A B C D

9 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 9 Logic Gates & Symbols Note: gates can have more than two inputs. Inverter (=NOT) inverts 0 to 1 and 1 to 0 AND gate c is 1 only if both a and b are 1 a b c OR gate c is 1 if either a or b is 1 a b c NAND gate c is 0 only if both a and b are 1 a b c NOR gate c is 0 if either a or b are 1 a b c

10 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 10 De Morgan’s Law A and B = not((not A) or (not B)) A or B = not((not A) and (not B)) Completeness  AND, OR and NOT are sufficient to represent any truth table.  Actually: AND & NOT, or OR & NOT are separately sufficient.  So: all we need are NOR or NAND gates. = =

11 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 11 Representation of Logic Functions A logic function can be represented as  a truth table  a logic expression  a logic circuit Example abcdf 00000 00010 00101 00111 01000 01010 01101 01111 10000 10011 10100 10111 11000 11011 11101 11111 b a c d f

12 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 12 Types of Logic Structures  Two types of logic structures (devices)  Storage structures: permit the storage of information (1 bit).  Decision structures: can make a decision but do not remember what it was: gates belong to this category.  Combinational logic  a logic structure is combinational if it is constructed from decision elements only: gates or other combinational logic structures.  the output of a combinational logic structure depends strictly on its current input.  Three examples  Decoder  Multiplexer (MUX)  Full adder

13 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 13 Decoder  An n input decoder has 2 n outputs.  Output i is 1 iff the binary value of the n-bit input is i.  At any time, exactly one output is 1, all others are 0. 1, iff A,B is 00 A B 1, iff A,B is 01 1, iff A,B is 10 1, iff A,B is 11 i = 0 i = 1 i = 2 i = 3

14 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 14 Multiplexer (MUX)  In general, a MUX has  2 n data inputs  n select (or control) lines  and 1 output.  It behaves like a channel selector. A 4-to-1 MUX: Out takes the value of A,B, C or D depending on the value of S (00, 01, 10, 11) S[1:0] ABCD Out ABCD S0S0 S1S1

15 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 15 Adder Half Adder  2 inputs  2 outputs: sum and carry Full Adder  performs the addition in column i  3 inputs: a i, b i and c i  2 outputs: s i and c i+1  c i is the carry in from bit position i-1  c i+1 is the carry out to bit position i+1 Half-adder truth table

16 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 16 Gate Level Full Adder

17 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 17 Full Adder - Expressions where - verify that this corresponds to the gate-level implementation.

18 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 18 A 4-bit Ripple-Carry Adder

19 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 19 Carry Lookahead Addition We can pre-compute the carry  The carry in bit 4 (C 4 ) is 1 if any two of A 3, B 3 or C 3 are 1.  P 3 is called the propagate bit, and G 3 the generate bit  So every carry bit can be pre-computed using all the previous inputs.  Pre-computation can be done in 2 gate delays.

20 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 20 Storage Elements: R-S Latch The R-S Latch The output (a) of the R-S latch can be set to 1 by momentarily setting S to 0 while keeping R at 1. If S is set to 1 the output stays at 0. 1 0 Conversely, the output can be set to 0 by keeping S at 1 and momentarily setting R to 0. When R is set back to 1, the output stays at 0. 1 0 0 1 0 1 The flip-flop (R-S latch) is a bi-stable element

21 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 21 Storage Elements: Gated D Latch The R-S Latch The gated D larch is an extension of the R-S latch Two inputs: data (D) and write enable (WE) When the WE (write enable) is set to 1, the output of the latch is set to the value of D. The output is held until WE is “asserted” (set to 1) again.

22 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 22 Registers A 4-bit register made of four D latches

23 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 23 Memory - 1 Address Space n bits allow the addressing of 2 n memory locations.  Example: 24 bits can address 2 24 = 16,777,216 locations (i.e. 16M locations).  If each location holds 1 byte then the memory is 16MB.  If each location holds one word (32 bits = 4 bytes) then it is 64 MB. A large number of addressable fixed size locations

24 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 24 Memory - 2 Addressability  Computers are either byte or word addressable - i.e. each memory location holds either 8 bits (1 byte), or a full standard word for that computer (typically 32 bits, though now many machines use 64 bit words).  Normally, a whole word is written and read at a time:  If the computer is word addressable, this is simply a single address location.  If the computer is byte addressable, and uses a multi-byte word, then the word address is conventionally either that of its most significant byte (big endian machines) or of its least significant byte (little endian machines).

25 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 25 Building a Memory Each bit  is a gated D-latch Each location  consists of w bits (here w = 1)  w = 8 if the memory is byte addressable Addressing  n locations means log 2 n address bits (here 2 bits => 4 locations)  decoder circuit translates address into 1 of n addresses WE A[1:0] D

26 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 26 Memory Example A 2 2 by 3 bits memory: two address lines: A[1:0] three data lines: D[2:0] one control line: WE One gated D-latch

27 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 27 Using Memory Building Blocks  Building an 8K byte memory using chips that are 2K by 4 bits. CS = chip select: when set, it enables the addressing, reading and writing of that chip. This is an 8KB byte addressable memory d e c o d er CS A10-A0 A12-A11 2K x 4 bits

28 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 28 Memory One Word Wide Use the previous memory block of 8K x 1 byte to build a memory that is 64K words, with each location one word of 32 bits.  what are the address lines if the memory is word addressed? or byte addressed? A? - A? d e c o d er A? - A? 8K x 1B

29 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 29 Finite-State Machines  Output is a function of the input and the state  The function is computed by the combinatorial logic circuit  The state is stored in the storage element  The state is also a function of itself and the input Combinational Logic Circuit Storage Element output input

30 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 30 FSM Example  Three groups of lights to be lit in a sequence: group 1 on, groups 1 & 2 on, all groups on, all off.  The lights are on only if the main switch is on.  Four states: so we need two bits to identify each state. DETOUR Combinational Logic Circuit Two bit Storage switch clock 2 2 out1 out2 out3 all on grp 1,2 on all off grp 1 on 1 1 0 0 0 1 0,1 01 10 11 00 S d[1:0]

31 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 31 FSM Example When is group 1 on?  in states 01, 10 and 11 - but only when the switch is on! When do we switch to the next state?  at every clock cycle the two bits are updated  d[1:0] is the state at the next clock cycle; it is a function of the input (switch) and the current state.  can you come up with a logic expression for d 0 and d 1 ?

32 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 32 The LC-2 as a Finite State Machine

33 Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. Slides prepared by Walid A. Najjar & Brian J. Linard, University of California, Riverside 3 - 33 Data Path of the LC-2

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