2. 2 Systems Architecture, Fifth Edition Chapter Goals Describe the system bus and bus protocol Describe how the CPU and bus interact with peripheral devices Describe the purpose and function of device controllers Describe how interrupt processing coordinates the CPU with secondary storage and I/O devices

3. 3 Systems Architecture, Fifth Edition Chapter Goals (continued) Describe how buffers, caches, and data compression improve computer system performance

4. 4 Systems Architecture, Fifth Edition

5. 5 System Bus Connects CPU with main memory and peripheral devices Set of data lines, control lines, and status lines Bus protocol –Number and use of lines –Procedures for controlling access to the bus Subsets of bus lines: data bus, address bus, control bus

6. 6 Systems Architecture, Fifth Edition

7. 7 Bus Clock and Data Transfer Rate Bus clock pulse –Common timing reference for all attached devices –Frequency measured in MHz Bus cycle –Time interval from one clock pulse to the next Data transfer rate –Measure of communication capacity –Bus capacity = data transfer unit x clock rate

8. 8 Systems Architecture, Fifth Edition Bus Protocol Governs format, content, timing of data, memory addresses, and control messages sent across bus Every peripheral device must follow the protocol rules. The bus protocol has a relationship with the capacity of the bus (maximum data transfer rate). For example the Hard Disk begin reading when it receives a control signal from the CPU, and it may return an acknowledgment to the CPU, rather than the data transferred. All of the previous need a separate bus cycle, then it consumes from the over all bus cycles of the PC.

9. 9 Systems Architecture, Fifth Edition The bus protocol regulates bus access to prevent devices from interfering with one another. If two devices attempt to send a message at the same time, this message will collide and generate electrical noise. To prevent the previous problem, there are two possible solutions for the relationship of the CPU and the other peripherals of the computer.

10. 10 Systems Architecture, Fifth Edition The first is Master-Slave approach: –The CPU is the bus master and the other devices are bus slaves. –Here, no device other than the CPU can access the bus except in response to an explicit instruction from the CPU. –So, there will be no collision because the CPU will wait the response of a device before it sends a command for other device. –(CPU is the cop). –This method has main problem, in that if two devices want to exchange data, this must be passed by the CPU, which slow down the performance of the CPU.

11. 11 Systems Architecture, Fifth Edition Peer-to-Peer approach: –Here the devices can exchange data between each others directly without the control of the CPU. –This could be done by Direct Memory Access (DMA) or Peer-to-peer buses. –In the DMA, there will be a device called DMA controller that attached to the bus and to the main memory. –The DMA plays the master of the bus when there will be data exchange between memory and other I/O devices. –While DMA manages bus traffic, the CPU can make computations (increase CPU performance).

12. 12 Systems Architecture, Fifth Edition –In a peer-to-peer, any device can assume control of the bus or act as bus master for transfer to other devices. –Single bus master will be chosen when several devices want to be master. –There will be a bus arbitration unit attached to the bus to decide which device(s) must wait when multiple devices want to become master.

13. 13 Systems Architecture, Fifth Edition Logical and Physical Access Not wanted.

14. 14 Systems Architecture, Fifth Edition Physical access: System bus is usually physically implemented on a large printed circuit board with attachment points for devices.

15. 15 Systems Architecture, Fifth Edition Logical access: The device, or its controller, translates linear sector address into corresponding physical sector location on a specific track and platter.

16. 16 Systems Architecture, Fifth Edition Device Controllers Storage and I/O devices are normally connected to the system bus by device controller. Device controller performs the following: –Implement the bus interface and access protocols –Translate logical addresses into physical addresses –Enable several devices to share access to a bus connection

17. 17 Systems Architecture, Fifth Edition

18. 18 Systems Architecture, Fifth Edition The device controller translates all of the signals come to the device to appropriate commands. And similarly, it translates the status and actions of the device to a proper signals that transmitted by the system bus. The device controller translates the logical addresses to physical ones, for example a disk controller converts logical access to a specific disk sector within a linear address space into a command to read from a specific head, track and sector.

19. 19 Systems Architecture, Fifth Edition Device controller can connect multiple peripheral devices to share single bus port. Buses must be fast enough to allow multiple connections of devices.

20. 20 Systems Architecture, Fifth Edition Mainframe Channels Advanced type of device controller used in mainframe controllers Compared with device controllers: –Greater data transfer capacity –Larger maximum number of attached peripheral devices –Greater variability in types of devices that can be controlled

21. 21 Systems Architecture, Fifth Edition SCSI (Small Computer System Interface) Family of standard buses designed primarily for secondary storage devices Implements both a low-level physical I/O protocol and a high-level logical device control protocol

22. 22 Systems Architecture, Fifth Edition

23. 23 Systems Architecture, Fifth Edition

24. 24 Systems Architecture, Fifth Edition Desirable Characteristics of a SCSI Bus Non-proprietary standard High data transfer rate Peer-to-peer capability High-level (logical) data access commands Multiple command execution Interleaved command execution

25. 25 Systems Architecture, Fifth Edition Secondary storage and I/O devices have slower data transfer rates than the CPU.

26. 26 Systems Architecture, Fifth Edition Interrupt Processing CPU is much more faster than I/O devices because of the mechanical motions. If the CPU waits for an I/O device to complete its task, a lot of CPU cycles will lost (Wait State). To prevent such insufficient use of the CPU, peripheral devices communicate with the CPU by interrupt signals. Interrupt is a signal sent by the peripheral to the CPU that something occurs, to make the CPU to perform a program or do something.

27. 27 Systems Architecture, Fifth Edition Part of the CPU is responsible to keep monitoring the bus signals for interrupts, and store these signals in an interrupt register. The interrupt signal is a numeric value called an interrupt code, usually equals to the bus port number of the peripheral sending the interrupt. When the control unit notices a non zero value in the interrupt register, the CPU suspends its current process, zeros the register, executes the process related to the interrupt, and then returns back to continue the suspended process.

28. 28 Systems Architecture, Fifth Edition Interrupt Handlers Interrupts are not related to hardware only, they can be used to perform programs also. OS uses interrupts in handling programs, for example if a value read by keyboard have to be sent for a running program, the keyboard sends an interrupt for the OS to send the data to the application.

29. 29 Systems Architecture, Fifth Edition Interrupt handler is part of the OS to process interrupts. When CPU detects interrupt, it executes a master interrupt handler program called supervisor to handle the interrupt.

30. 30 Systems Architecture, Fifth Edition Multiple Interrupts What will happen if more than interrupt occurs at the same time? There will be priorities. Interrupts can be classified into set of categories: –I/O event –Error condition –Service request

31. 31 Systems Architecture, Fifth Edition I/O interrupts are used to notify the CPU that data are ready to be transferred to or from an I/O device. Error condition interrupts are used to indicate errors that occurred during the normal processing. Error interrupts can be generated by software (for example, when attempting to open a non-existent file) or by hardware (when attempting to divide by zero or when battery power in a portable computer nearly exhausted).

32. 32 Systems Architecture, Fifth Edition Service Request Interrupts: done by the different applications when they need a service from the OS. An Interrupt code is given for every application, and when an application wants to make an interrupt, it places its code in the interrupt register, and the CPU handles it. The OS groups the interrupts by importance or priority. For example, error conditions are given high priority. Critical errors like shutdown are given the highest priority. The priority is important in determining if the coming priority should stop the current CPU process or not.

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34. 34 Systems Architecture, Fifth Edition Stack When the CPU executes more than one process, and an interrupt(s) occur, how the CPU can remember where it was, and continue the execution with the last values it was using? To do that, stack is used. Stack is an area of storage that is accessed in a last-in, first-out (LIFO)basis.

35. 35 Systems Architecture, Fifth Edition Like stack of dishes. Items can be added or removed from the top of the stack. In computer, stack is a primary storage area that holds register values of interrupted processes or programs. When a process is interrupted, values in CPU registers are added to the stack (Push). The saves values are called machine state. When an interrupt handler finishes executing, the CPU removes values on the top of the stack and loads them back to the CPU registers. (POP).

36. 36 Systems Architecture, Fifth Edition It is sometimes possible for a stack to be full, and can’t get more values (stack overflow). The size of the stack determines the number of possible interrupted applications. Stack Pointer is a special purpose register that used to indicate the next empty space in the stack.

37. 37 Systems Architecture, Fifth Edition Buffers and Caches Improve overall computer system performance by employing RAM to overcome mismatches in data transfer rate and data transfer unit size

38. 38 Systems Architecture, Fifth Edition Buffers Small storage areas (usually DRAM or SRAM) that hold data in transit from one device to another Use interrupts to enable devices with different data transfer rates and unit sizes to efficiently coordinate data transfer Buffer overflow

39. 39 Systems Architecture, Fifth Edition

40. 40 Systems Architecture, Fifth Edition Computer system performance improves dramatically with larger buffer.

41. 41 Systems Architecture, Fifth Edition Diminishing Returns When multiple resources are required to produce something useful, adding more and more of a single resource produces fewer and fewer benefits Applicable to buffer size

42. 42 Systems Architecture, Fifth Edition Law of diminishing returns affects both bus and CPU performance

43. 43 Systems Architecture, Fifth Edition Cache Differs from buffer: –Data content not automatically removed as used –Used for bidirectional data –Used only for storage device accesses –Usually much larger –Content must be managed intelligently Achieves performance improvements differently for read and write accesses

44. 44 Systems Architecture, Fifth Edition Write access: Sending confirmation (2) before data is written to secondary storage device (3) can improve program performance; program can immediately proceed with other processing tasks.

45. 45 Systems Architecture, Fifth Edition Read accesses are routed to cache (1). If data is already in cache, it is accessed from there (2). If data is not in cache, it must be read from the storage device (3). Performance improvement realized only if requested data is already waiting in cache.

46. 46 Systems Architecture, Fifth Edition Cache Controller Processor that manages cache content Guesses what data will be requested; loads it from storage device into cache before it is requested Can be implemented in –A storage device storage controller or communication channel –Operating system

47. 47 Systems Architecture, Fifth Edition Cache Primary storage cacheSecondary storage cache Can limit wait states by using SRAM cached between CPU and SDRAM primary storage Level one (L1): within CPU Level two (L2): on-chip Level three (L3): off-chip Gives frequently accessed files higher priority for cache retention Uses read-ahead caching for files that are read sequentially Gives files opened for random access lower priority for cache retention

48. 48 Systems Architecture, Fifth Edition Intel Itanium ® 2 microprocessor uses three levels of primary storage caching.

49. 49 Systems Architecture, Fifth Edition Processing Parallelism Increases computer system computational capacity; breaks problems into pieces and solves each piece in parallel with separate CPUs Techniques –Multicore processors –Multi-CPU architecture –Clustering

50. 50 Systems Architecture, Fifth Edition Multicore Processors Include multiple CPUs and shared memory cache in a single microchip Typically share memory cache, memory interface, and off-chip I/O circuitry among the cores Reduce total transistor count and cost and provide synergistic benefits

51. 51 Systems Architecture, Fifth Edition

52. 52 Systems Architecture, Fifth Edition Multi-CPU Architecture Employs multiple single or multicore processors sharing main memory and the system bus within a single motherboard or computer system Common in midrange computers, mainframe computers, and supercomputers Cost-effective for –Single system that executes many different application programs and services –Workstations

53. 53 Systems Architecture, Fifth Edition Scaling Up Increasing processing by using larger and more powerful computers Used to be most cost-effective Still cost-effective when maximal computer power is required and flexibility is not as important

54. 54 Systems Architecture, Fifth Edition Scaling Out Partitioning processing among multiple systems Speed of communication networks; diminished relative performance penalty Economies of scale have lowered costs Distributed organizational structures emphasize flexibility Improved software for managing multiprocessor configurations

55. 55 Systems Architecture, Fifth Edition High-Performance Clustering Connects separate computer systems with high- speed interconnections Used for the largest computational problems (e.g., modeling three-dimensional physical phenomena)

56. 56 Systems Architecture, Fifth Edition Partitioning the problem to match the cluster architecture ensures that most data exchange traverses high-speed paths.

57. 57 Systems Architecture, Fifth Edition Compression Reduces number of bits required to encode a data set or stream Effectively increases capacity of a communication channel or storage device Requires increased processing resources to implement compression/decompression algorithms while reducing resources needed for data storage and/or communication

58. 58 Systems Architecture, Fifth Edition Compression Algorithms Vary in: –Type(s) of data for which they are best suited –Whether information is lost during compression –Amount by which data is compressed –Computational complexity Lossless versus lossy compression

59. 59 Systems Architecture, Fifth Edition Compression can be used to reduce disk storage requirements (a) or to increase communication channel capacity (b).

60. 60 Systems Architecture, Fifth Edition MPEG standards address recording and encoding formats for both images and sound.

61. 61 Systems Architecture, Fifth Edition Summary How the CPU uses the system bus and device controllers to communicate with secondary storage and input/output devices Hardware and software techniques for improving data efficiency, and thus, overall computer system performance: bus protocols, interrupt processing, buffering, caching, and compression