1. Architecture and Dataflow Overview LHCb Data-Flow Review September 2001 Beat Jost Cern / EP

2. Beat Jost, Cern Data-Flow Review Sep. 2001 2 Overall Architecture Read-out Network (RN) RU 6-15 GB/s 50 MB/s Variable latency L2 ~10 ms L3 ~200 ms Control & Monitoring LAN Read-out units (RU) Timing & Fast Control Level-0 Front-End Electronics Level-1 VELO TRACK ECAL HCAL MUON RICH LHCb Detector L0 L1 Level 0 Trigger Level 1 Trigger 40 MHz 1 MHz 40-100 kHz Fixed latency 4.0  s Variable latency <2 ms Data rates 40 TB/s 1 TB/s 1 MHz Front End Links Trigger Level 2 & 3 Event Filter SFC CPU Sub-Farm Controllers (SFC) Storage Throttle Front - EndMultiplexers(FEM) Functional Components Timing and Fast Controls (TFC) Front-End Multiplexing (FEM) Readout Unit (RU) Readout Network (RN) Sub-Farm Controllers (SFC) CPU Farm External Interfaces/Sub-Systems Front-End Electronics Triggers (Level-0 and Level-1) Accelerator and Technical Services (Controls & Monitoring)

3. Beat Jost, Cern Data-Flow Review Sep. 2001 3 Functional Requirements qTransfer the physics data from the output of the Level-1 Electronics to the the CPU farm for analysis and later to permanent storage qDead-time free operation within the design parameters qReliable and ‘error-free’, or at least error-detecting qProvide Timing information and distribute trigger decisions qProvide monitoring information to the controls and monitoring system qSupport independent operation of sub-parts of the system (partitioning)

4. Beat Jost, Cern Data-Flow Review Sep. 2001 4 Performance Requirements LHCb in NumbersLHCb DAQ in Numbers The System will be designed against the nominal Level-1 trigger rate of 40 kHz, with a possible upgrade path to a Level-1 trigger rate of 100 kHz. Lead-time ~6-12 months  Scalability

5. Beat Jost, Cern Data-Flow Review Sep. 2001 5 General Design Criteria qUniformity ãAs much commonality as possible among sub-systems and sub- detectors åReduced implementation effort åReduced maintenance effort (bug fixed once is fixed for all) åReduced cost qSimplicity ãKeep individual components as simple as possible in functionality åMinimize probability of component failure åImportant for large numbers ãKeep protocols as simple as possible to maximize reliability qStrict separation of controls and data paths throughout the system  Possibly at the cost of increased performance requirements in certain areas

6. Beat Jost, Cern Data-Flow Review Sep. 2001 6 Specific Choices (1) qOnly point-to-point links, no shared buses across modules… ãFor the physics data obvious ãFor controls desirable ãClear separation between data path and control path qLink and Network Technology ã(optical) Gb Ethernet as uniform technology from the output of the Level-1 electronics to the input to the SFC, because of its (expected) abundance and longevity (15+ years) qReadout Protocol ãPure push-trough protocol throughout the system, i.e. every source of data sends them on as soon as available ãOnly raw Ethernet frames, no higher-level network protocol (IP) ãNo vertical nor horizontal communications, besides data (->Throttle mechanism for flow control)

7. Beat Jost, Cern Data-Flow Review Sep. 2001 7 Specific Choices (2) qIntegrated Experiment Control System (ECS) ãSame tools and mechanisms for detector and dataflow controls ãPreserving operational independence qCrates and Boards ãThe DAQ components will be housed in standard LHCb crates (stripped-down VME crates) ãThe Components will be implemented on standard LHCb boards (9Ux400mm VME-like, without VME slave interface)

8. Beat Jost, Cern Data-Flow Review Sep. 2001 8 Constraints and Environment qThe DAQ system will be located at Point 8 of the LHC ãSome equipment will be located underground… åall the Level-1 electronics åFEM/RU? å(parts) of readout network? ã…and some on the surface å(parts) of the readout network åSFCs åCPU-farm åComputing infrastructure (CPUs, Disks, etc…) åControl Room Consoles etc. ãNo DAQ Equipment will be located in radiation areas qIssues ãCooling/Ventilation ãFloor-space Optical GbEthernet allows free distribution

9. Beat Jost, Cern Data-Flow Review Sep. 2001 9 Summary qDesign criteria ãSimplicity, Commonality, Uniformity åPotentially with higher cost in certain areas åLot of advantages in operation of the system qDesigned around Gb Ethernet as basic link technology throughout the system (except individual farm nodes) qPure push protocol without higher network protocol qNo shared buses for neither data nor controls qControls and data paths are separated throughout the system