1. MAKING A “MODEL” BOB PEDDENPOHL MODELING MANAGER CYPRESS MODELING CENTER LEXINGTON, KY

2. 2 Cypress Confidential OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

3. 3 Cypress Confidential DESIGN KIT MAKES MONEY DESIGN KIT (CAD, R&D)PRODUCT ($) PRE-SILICON WORKSILICON QUAL MODELSCIRCUIT DESIGN SCHEMATICS LAYOUTS DRC LVS E-TEST MODULES TEST CHIP TAPEOUT PRODUCT PLANS MEAS. VTH IDS METAL THICK ILD THICK SPICE RCX MARKET NEEDS PRODUCT SPECS CIRCUIT SCHEMATIC LAYOUT

4. 4 Cypress Confidential DESIGN KIT MAKES MONEY DESIGN KIT (CAD, R&D)PRODUCT ($) PRE-SILICON WORKSILICON QUAL MODELSCIRCUIT DESIGN SCHEMATICS LAYOUTS DRC LVS E-TEST MODULES TEST CHIP TAPEOUT PRODUCT PLANS MEAS. VTH IDS METAL THICK ILD THICK SPICE RCX MARKET NEEDS PRODUCT SPECS CIRCUIT SCHEMATIC LAYOUT

5. 5 Cypress Confidential OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

6. 6 Cypress Confidential INTRODUCTION: MODELS GENERIC DEFINITION MAN MADE EXPRESSIONS TO REPRESENT MOTHER NATURE VLSI DESIGN DEFINITION MODELS = DESIGNERS PERCEPTION OF TECHNOLOGY ENGINEERING DEFINITION MODELS = PHYSICAL EQUATIONS + PARAMETERS Ids = BETA (Vgs-VT)^2 where VT = 0.6 BETA = w/l*COX*MOBILITY = 1E-6

7. 7 Cypress Confidential INTRODUCTION:TYPES OF MODELS SIMULATION MODELS TABLE LOOKUP SIMULATORS ACCESS MEASURED DC/AC DATA IN A TABULAR FORM ANALYTICAL (OR COMPACT) ANALYTICAL OR COMPACT DEVICE MODELS BASED PRIMARILY ON DEVICE PHYSICS. FITTING PARAMETERS INTRODUCED TO IMPROVE ACCURACY NUMERICAL NUMERICAL SOLUTION OF DEVICE CHARACTERISTIC

8. 8 Cypress Confidential SCHEMATICS USE BSIM COMPACT MODELS

9. 9 Cypress Confidential INTRODUCTION: MODELS LIMITATIONS IDEAL VS REALITY IDEAL DESIGN SIMULATIONS EXACTLY EQUAL SILICON MEASUREMENTS REALITY MODEL NOT PERFECT MODEL HAS ACCURACY LIMITATIONS GOOD DESIGNER UNDERSTANDS MODEL LIMITATIONS NEED TO MODEL PROCESS VARIATIONS NEED MODELS QUICKLY TO ENABLE DESIGNERS

10. 10 Cypress Confidential OUTLINE WHAT DOES CY KENTUCKY DO? WHAT IS A BSIM SPICE MODEL? HOW TO MAKE A MOS SPICE MODEL?

11. 11 Cypress Confidential WHAT MODELS USED AT UK? WHAT CY TECHNOLOGY DID YOU USE? RAM7: Wmin/Lmin = 0.42/0.20um, Vcc=1.8V, Idrive = 9.99 mA WHEN WAS TECHNOLOGY QUALIFIED? MODEL FROZEN Q302 WHAT TYPE OF MOSFETS? LV MOS (NSHORT/PSHORT), LVT PMOS (PLOWVT) CELL FETS (NPASS, NPD, PPU) WHAT’S NSHORT ELECTRICAL TOX? JUNCTION DEPTH? TOX= 41 A, XJ = 0.1um

12. 12 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

13. 13 Cypress Confidential SELECT “GOLDEN” WAFER IDEAL: MODELING SILICON CLOSE TO NOMINAL REALITY: ~400+ PARAMETERS, ONLY MOST IMPORTANT ON TARGET NOMINAL MIN MAX WAFER

14. 14 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

15. 15 Cypress Confidential MEASUREMENTS: HARDWARE & SOFTWARE

16. 16 Cypress Confidential MEASUREMENTS: COMPLETE MOS FET DC (VTH0, RDSW) FET AC (CGDO,DLC) DIODE DC (JS,JSW) DIODE AC (CJ, CJSW)

17. 17 Cypress Confidential MEASUREMENTS: FET DC

18. 18 Cypress Confidential MEASUREMENTS: FET DC MODEL NEEDS SCALE WITHIN ALL GEOMETRY, TEMP

19. 19 Cypress Confidential MEASUREMENTS: DC FET QA, VTH VS. L MODEL ACCURACY MEASUREMENT ACCURACY CONDENSED DATA TRENDS Strong Halo, L dependence Halo with SCE Normal SCE

20. 20 Cypress Confidential MEASUREMENTS: DC FET QA, VTH VS. W MODEL ACCURACY MEASUREMENT ACCURACY CONDENSED DATA TRENDS LOCOS (+k3) STI (-k3)

21. 21 Cypress Confidential MEASUREMENTS: FET AC

22. 22 Cypress Confidential MEASUREMENTS: DIODE DC/AC REVERSE BIAS DC CHARACTERISTIC I_FORWARD ~mA I_Reverse ~ pA REVERSE BIAS AC CHAR.= f(CJA, CJP, EX,)

23. 23 Cypress Confidential MEASUREMENTS: TRANSIENT RING OSCILLATOR VALIDATION OF MODEL INO/P C9R10

24. 24 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

25. 25 Cypress Confidential WAFER CASE: DC MOS EXTRACTION MODEL = EQUATIONS + PARAMETERS EQUATIONS (BSIM3V3) + MODEL PARAMETERS = WAFER CASE MODEL Threshold Model Mobility Model Drive Current Channel Length Modulation Short Channel Effects

26. 26 Cypress Confidential WAFER CASE: MOS MODEL BINNING Long/Wide Constant Vt Narrow Width Effects (STI/LOCOS) Short Channel Effects (HALO/DIBL)

27. 27 Cypress Confidential WAFER CASE: AC FET + DIODE MODEL EXTRACTION MODEL = EQUATIONS + PARAMETERS EQUATIONS (BSIM3V3) + PARAMETERS (EXTRACTED FROM MEASUREMENTS) = MODEL (WAFER CASE) Accumulation Inversion Intrinsic Cap for Analog Design BSIM3 Limitation MOS DIODE IV MODEL MOS DIODE CV MODEL MOSFET CV MODEL

28. 28 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

29. 29 Cypress Confidential RO CAL: LAYOUT EXTRACTED SIMULATION VALIDATE CAD EXTRACTION RULES + MOS BSIM MODELS INO/P R10 LAYOUT (DESIGN DEP.) LAYOUT MODEL: (ILD, METAL THICK) C9 CALIBRE RCX CIRCUIT: FET DELAY + R interconnect + C interconnect SPICE MODELS RO SIMS = RO MEAS

30. 30 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

31. 31 Cypress Confidential CORNER MODELS WAFER CASE SIMULATIONS = WAFER MEASUREMENTS WHAT ABOUT PROCESS VARIATIONS? WILL MY DESIGN YIELD? NOMINAL MIN MAX WAFER

32. 32 Cypress Confidential CORNER MODELS REALITY EVERY SITE/WAFER/LOT/SPLIT IS DIFFERENT ( PROCESS VARIATIONS) WORKING WITH REALITY CORNERS: MODELING SPACE TO COVER ALL POSSIBILITIES (STATISTICALLY) IN PROCESS TEAM EFFORT TO GET GOOD YIELD FAB: +/-4 SIGMA E-TEST  99.99% WAFERS INSIDE MIN/MAX MODELING: MIN/MAX MODELS MATCH FAB LIMITS DESIGN: SIMULATE DESIGN WORKING AT MIN/MAX LIMITS ALL 3 GROUPS WORKING = GOOD PRODUCT YIELD NOMINAL MIN MAX tt.cor ss.cor wafer.cor ff.cor

33. 33 Cypress Confidential WHY 5 MOS CORNERS? VTs AT SS & FF = 70% SPEC RANGE VTs AT FS/SF = 100% SPEC RANGE fs sf ff ss VTXNS15 vs. VTXPS15 (V) (Vth @ W/L=25/0.15um) IDSNS15 vs. IDSPS15 (mA) Idrive (Vgs=Vds=Vcc) W/L=25/0.15um ss ff fs sf tt

34. 34 Cypress Confidential WHY CORNER METHODOLOGY IMPORTANT MODEL MUST MATCH DESIGN/FAB AGREED LIMITS FAB WANTS WIDE MIN/MAX LIMITS STATISTICAL PROCESS CONTROL (SPC) HOW GOOD DOES A PROCESS RUN WITHIN IT’S NOM/MIN/MAX DESIGN WANTS NARROW MIN/MAX LIMITS EASIER TO DESIGN SMALL PROCESS VARIATION  SMALLER SI AREA

35. 35 Cypress Confidential MODEL DEVELOPMENT PROCESS MEASUREMENT (DC, AC, TRAN) EXTRACT WAFER CASE MODEL RO MEAS = RO SIMS CENTER TO EDR NOMINAL (TT) SELECT “GOLDEN” WAFER SKEW MODELS (FF, SS, FS, SF) QA & RELEASE TO DESIGN

36. 36 Cypress Confidential QA: MODEL DOCUMENTATION MODEL SUMMARY TABLE MODEL ACCURACY IN SUB-THRESHOLD, GM ACCURACY

37. 37 Cypress Confidential

38. APPENDIX BOB PEDDENPOHL (PED) CYPRESS MODELING CENTER

39. 39 Cypress Confidential Applying the Corner Models Design Interconnect R tres, fres, sres Interconnect C tpar, fpar, spar r+c.mod Interconnects/Passives trtc, hrlc, lrhc FET Corners tt, ff, ss, sf, fs CellFET Corners ttcell, ffcell, sscell Temp coef of R C for various line/space Npass Nlatch Platch Nmos/Pmos Nthick/Pthick (HV) Diode PNP metal/contact/poly/diff Sheet resistances