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Building Cad Prototyping Tool for Emerging Nanoscale Fabrics Catherine Dezan Joined work between Lester( France.

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Presentation on theme: "Building Cad Prototyping Tool for Emerging Nanoscale Fabrics Catherine Dezan Joined work between Lester( France."— Presentation transcript:

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2 Building Cad Prototyping Tool for Emerging Nanoscale Fabrics Catherine Dezan (dezan@univ-brest.fr)dezan@univ-brest.fr Joined work between Lester( France ) and UMASS( USA )

3 European Nano Systems Conference, 12/03/2007 Université de Bretagne Occidentale(LESTER, CNRS) Catherine Dezan Loic Lagadec University of Massachusetts at Amherst Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Andras Moritz Contributors:

4 European Nano Systems Conference, 12/03/2007 Motivation  Bottom-up strategies -> more defective (10 -9 to 10 -7 failure rate in CMOS technology, 10 -2 to 10 -1 failure rate in emerging nanotechnologies) -> CAD tool should take this into account  Evolutive nanofabrics (Semiconductor Nanowire -> Carbone Nanotube) needs generic CAD tool for a quick adaptation

5 European Nano Systems Conference, 12/03/2007 Outline of the talk  Defective Hybrid Nanofabrics  Proposal of prototyping tool based on Nanofabric specification Design flow Models for Nanofabric Specification Transformations based on Nanofabric models Fault-tolerant transformations  Conclusion

6 European Nano Systems Conference, 12/03/2007 Emerging Nanofabrics NASIC[ Moritz 2004 ], NanoPla[ Dehon2005 ], CMOL[ Likharev 2005 ], FPNI[ Snider2007 ] Possible manufacturing procedures (demonstrated for every step, but not yet the whole process) Our references to nanofabrics, based on progress of Semiconductor Nanowire manufacturing [ Lieber2007 ] are hybrid CMOS/Nano fabrics:

7 European Nano Systems Conference, 12/03/2007 Existing CAD tools are specific  These nanofabrics propose a range of test applications on their nano support Ex: microprocessor (NASIC), Neuromorphic networks(CMOL), general purpose  Each specific fabric proposes its specific CAD tools: Ex:CMOL FPGA compiler, FPNI compiler, NanoPla CAD

8 European Nano Systems Conference, 12/03/2007 Towards a generic prototyping CAD tool Main features:  Generic CAD tool: not specific CAD tool adapted to a single Nanofabric  Based on Nanofabric Specification through models  Design flow from behavioral description towards symbolic layout  Fault-tolerant transformations

9 European Nano Systems Conference, 12/03/2007

10 Nanofabrics Specification through models Computational model Architectural model Technological model Fault model Abstractions of some nanofabric mechanism

11 European Nano Systems Conference, 12/03/2007 Computational and Architectural models Workshare between nano Interconnect(FPNI), Interconnect +computation (NanoPla,CMOL,NASIC) and its organization(2 or multi-level logic) CMOS I/O, specific gate(inv), control Structural and hierarchical organization of building components in tiles

12 European Nano Systems Conference, 12/03/2007 Technological and Fault models Physical constraints for place-and-route routines: -doping constraints (NASIC) -Connection constraints for reconfigurable fabric -Defect map Fault types with distribution (uniform/cluster) and rates: permanent defects (manufacturing process), stuck-on,stuck-off transistor, broken nanowire Transient faults ( internal noise, particle impact,.. ) Process variation( channel length, doping, wire thickness )

13 European Nano Systems Conference, 12/03/2007 (1) (2) (3)

14 European Nano Systems Conference, 12/03/2007 Behavioral transformations(1) In addition to classical high-level transformations, we take into account:  pre-partionning for Nano/CMOS transformation (according to the computational model)  fault-tolerant transformations(adding voting spec, Error correcting codes, transfert in CMOS) (according to fault model)

15 European Nano Systems Conference, 12/03/2007 Case study of NASIC fabric(1) Computational model: CMOS limited for control signal, computation with 2 level logic Fault model: permanent, transient, uniform/cluster Fault-tolerant transformation: Data encoded in BCH codes in order to build redundant logic ( Hamming distance related to fault rate ) 4bits -> 7bits with BCH(7,4,1) Rebuild computation DAG

16 European Nano Systems Conference, 12/03/2007 Synthesis and structural transformations(2)  Synthesis with an external tool (SIS,ABC) directives are produced by the computational model and architectural model (ex: 2 level logic -> pla synthesis)  Structural transformations to add specific circuitry (decodeur for I/O, signal restoration, additional CMOS circuitry..) related to the architectural model  Fault-tolerant transformations based on the structural representation of the application: structural copies defined at fine grain or coarse grain( using voters- in CMOS) related to fault model

17 European Nano Systems Conference, 12/03/2007 Example of fault-tolerant transformations at structural level (2) Architectural model: 2D grid with FET, microwires around tiles External tool for logic synthesis (SIS, ABC) S=f(x,y,z) Fault tolerant transformation: structural redundancy at fine grain pla x y z and or and’ or’ s

18 European Nano Systems Conference, 12/03/2007 Yield projection(2) Fault-tolerant techniques produce different yield related to fault rate, types of fault and distribution -> need of iterations in flow design Integration of the yield simulator for NASIC

19 European Nano Systems Conference, 12/03/2007 Physical design (3) Transformations at this level include partitioning, placement and routing onto the nanofabric:  Reconfigurable fabrics have congestion problem for place- and-route due to the restriction of connections(adaptation of pathfinder algorithm is appropriate - feasibility proved with our previous experiment on FPGA CAD tool)  Generic heuristics like simulated annealing, clustering may be suitable for placement into tiles and between tiles -> custom adaptation is made using the technological model Possibility to add new custom routines to achieve better results

20 European Nano Systems Conference, 12/03/2007 Symbolic layout for NASIC(3) Technological model: Doping constraints Program Counter + Rom + decoder Register file + Alu Place-and-route routines with fixed size of tiles

21 European Nano Systems Conference, 12/03/2007 Conclusion  Proposal of a generic tool based on Nanofabric Specification  Proposal of adequate models correlated to transformations  One instance based on NASIC fabric was developped

22 European Nano Systems Conference, 12/03/2007 Future investigations  Investigating on more detailed models and their automatic integration in the generic framework  Adding more fault-tolerant transformations and hybrid fabric related transformations (probabilistic computation and synthesis?)  More case studies to consolidate and validate the framework dezan@univ-brest.fr

23 European Nano Systems Conference, 12/03/2007 Thanks Catherine.Dezan@univ-brest.fr

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