1. CPU Interfacing
Memory

2. D0 - D7 D8 - D15 SRAMs Y0 Y1 Y2 Y3 A17 Y4 A0 A18 Y5 A1 A19 Y6 A2 Y7 G1CS OE WE
SRAMs A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A17
A18
A19 A0 A1 A2 G1 G2 RD RD RD RD WR WR WR WR A0
DEN
D8 - D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE
A1-A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE WE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A17
A18
A19 A0 A1 A2 G1 G2 RD RD RD RD WR WR WR WR
BHE
DEN

3. D0 - D7 D8 - D15 EPROMs Y0 Y1 Y2 Y3 A17 Y4 A0 A18 Y5 A1 A19 Y6 A2 Y7CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A17
A18
A19 A0 A1 A2 G1 G2 RD RD RD RD A0
DEN
D8 - D15
A1-A16 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
A11
A12
A13
A14
A15 D0 D1 D2 D3 D4 D5 D6 D7 CS OE Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
A17
A18
A19 A0 A1 A2 G1 G2 RD RD RD RD
BHE
DEN

4. Notes Each Memory Module Size: A0-A15  64K Total SRAM: 8*64k=512k
Total EPROM: 8*64k=512k
SRAM Adresses: 0 – 0x7FFFF
EPROM Addresses: 0x80000 – 0xFFFFF

5. Parallel Port Interfacing
Input/ Output Ports
Introduction to 8255

6. Parallel Ports Necessity Applications: Motor Driving Data Printing
Lights on/off
Switches open/close
Actuator Control
Solenoid Valve Control
Communication

7. Parallel I/O Examples CPU I/O Memory Devices
in al, 40h ;al gets 1 byte from port 40h
in ax, ;ax gets 2 bytes from port ffh
in al, dx ;ax gets 1 byte from port address in dx
in ax, dx ;ax gets 2 bytes from port addr. in dx
out 80h, al ;send contents of al to port 80h
out dx, ax ;send contents of ax to port addr. in dx
I/O
Devices
Memory
CPU
Data Bus
Address Bus
Control Bus
Address/Data Bus is Shared - Control Bus Indicates I/O or Memory

8. Parallel I/O I/O port similar to memory address
x86 uses M/IO control bus output to “signal” I/O NOT memory
Port address (number) 16 bits long (0000h – ffffh)
Port width is 8 or 16 bits (parallel)
Memory Space
20 (8086) or
32 (pentium)
bit memory
address
16 bit I/O
port address
I/O Space
M/IO = 1
M/IO = 0

9. I/O Port Addressing Modes
Two addressing modes
1) Immediate port address
- Can only be 1 byte immediate address
- Can only address ports 00h through ffh
2) Port address present in DX
- Can address all ports 0000h through ffffh
Can only use DX for port addresses
Can only use AL,AX for port data

10. I/O Data Transfer 386+ in al, 40h ;al gets 1 byte from port 40h
in ax, ;ax gets 2 bytes from port ffh
in al, dx ;ax gets 1 byte from port address in dx
in ax, dx ;ax gets 2 bytes from port addr. in dx
out 80h, al ;send contents of al to port 80h
out dx, ax ;send contents of ax to port addr. in dx
386+
insb 72 ;receive byte string from port 72
;store in location at es:di
insw dx ;receive word string from port addr. in dx
insd dx ;receive double word string
outsb ffh ;send byte string to port 255
;source string located in memory at ds:si
outsw dx ;send word string to port addr. in dx
outsd dx ;send double word string to port

11. Input I/O Port Interface

12. Output I/O Port Interface

13. Standard IBM AT I/O Memory Map
ALSO:
0000h-03ffh Reserved for Computer System
0400h-0fffh Available for User
00f8h-00ffh Reserved for Intel
00f8h-00fdh Used for x87 FPU
BE CAREFUL WHICH PORTS
YOU INTERFACE TO!!!

14. Memory Mapped I/O
Possible to design address decoder to “divert” read or write to a device instead of memory
Replace memory chip with set of latches (CPU Write) and set of tri-state buffers (CPU Read)
In hardware, appears to be I/O port interface
In software, appears to be memory location
Use mov instead of in, out
Advantage is large variations in addressing modes
Disadvantage is particular memory address can NEVER be used for data storage

15. Packaged I/O Interface Circuits
Several developed by Intel to ease design burden
Provide a complete I/O interface on a single chip
Examples of common I/O interface chips:
8255A Programmable Peripheral Interface (PPI)
8259 Programmable Interrupt Controller (PIC)
8253/4 Programmable Interval Timer (PIT)
8237 Programmable DMA Controller
IBM PC/XT had these chips on system board
Modern PCs have functionality included in system chipset

16. 8255 PPI (Programmable Peripheral Interface) (Parallel Port Interface)
Data
Port A RD 8
Port B WR 4
RESET { CH
Port C CS 4 CL A1 A0

17. Addressing the 8255 A1 A0 = 00 Port A ; IN, OUT 8 bits at a time
= 01 Port B ; IN, OUT 8 bits at a time
= 10 Port C ; IN, OUT 8 bits at a time
= 11 Control Register; Write ONLY!
Addressing Example
PORTA EQU 0224h ;Port A 8255
PORTB EQU 0225h ;Port B 8255
PORTC EQU 0226h ;Port C 8255
STAT EQU 0227h ;Control Port

18. Interfacing the 8255 20 8086 A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11+
Address and Data lines are multiplexed in the 8086
Address Only
Address/Data
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

19. Address and Data Buses 20 8086 Address Latch 20-bit address bus ALE
ALE is Address Latch Enable 16
Data Transceiver
16-bit data bus

20. { Addressing the 8255 IO/M 8-bit data bus 8 Data Port A
Logic
Circuit
A15
-A2
IO/M 8 4
Port A
Port B CH CL {
Port C
Data WR RD CS
RESET A1 A0
8-bit data bus
20-bit address bus A1 A0

21. Logic Circuit Inputs to the Logic Circuit
address lines A15 - A2 (the I/0 address space is 216 addresses, and A1 and A0 are used for the chip’s address lines)
the 8086’s IO/M line HIGH denotes an IO instruction (IN, OUT) LOW denotes a memory access instruction (i.e., MOV)
Output of the logic circuit
a single low value from the 15 inputs (a NAND or OR gate) to activate the Chip Select
The connections for A15-A2 fix the chip’s address in I/O space

22. 8088 pins
The 8088 is a 16-bit microprocessor:
Internal registers and buses are 16 bits wide
12 addresslines
8 address/data lines
RD and WR
IO/M

23. Minimum mode
In minimum mode, the 8086/8088 is the only microprocessor in the circuit. It can assume that it has control of memory, address, and data buses
In maximum mode, the 8086/8088 is configured for multiple microprocessors. The function of pins is changed to provide processor-to-processor communication

24. Reset
A single reset line is connected to all chips in the system (8088/8086, 8255, 8253, etc.)
Reset puts the chip in a known state
Pushing the reset button on your computer generally activates RES pin of 8284 that outputs a high Reset pulse for a short period of time
On Reset, the 8088/8086 goes to fixed addresses (ROM chips) where boot sequence instructions are stored.

25. Basic Description of the 8255
Its three I/O ports (labeled A,B, and C) are programmed in groups of 12 pins :
Group A connections consist of port A (PA7-PA0) and the upper half of port C (PC7-PC4)
Group B consists of port B (PB7-PB0) and the lower half of port C(PC3-PC0)
The 8255 is selected by its CS pin for programming, for reading or writing to a port.
Register selection is accomplished through the A1 and A0 input pins, which select an internal register for programming or operation

26. 8255A PPI – Parallel I/O Interface

27. 8255A PPI – Assets and Capabilities
24 I/O lines in 3 8-bit port groups – A, B, C
A, B can be 8-bit input or output ports
C can serve as 2 4-bit input or output ports
3 modes of operation:
Mode 0: A, B, C simple input or output level sensitive ports
Mode 1: A, B input or output ports with strobe control in C
Mode 2: A is bidirectional with control/handshake in B and C
A, B can only change 1 byte at a time
C has individual bit set/reset capability
Advantage is non-dedicated circuit can change port configuration with software and no “glue logic”

28. Mode Selection of the 8255 Ports A, B, and C are used for I/O data.
The control register is programmed to select the operation mode of the three ports A, B, and C.
Mode 0 : simple I/O mode
Any of the ports A, B, CL and CU can be programmed as input or output.
No control of individual bits (all bits are out or all bits are in)
Mode 1 : Ports A and B can be used as input or output ports with handshaking.
Mode 2 : Port A can be used as bidirectional I/O port with handshaking

29. PPI Interface to CPU the PPI maps each of its 4 bytes
to an address, but all connect to
the same byte of the data bus; if
data bus is 1 byte wide, they are
consecutive addresses; if the bus
is 2 bytes wide, they are mapped
to alternate addresses; if the bus
is 4 bytes wide, …etc.

30. Programming/Controlling the PPI
8255A PPI has a “write-only” control register, accessed when PPI’s A0=A1=1 (note: not A0 and A1 of the address bus!)
When PPI is reset (by an active-high strobe on its RESET pin):
Default is A, B, C are mode 0 input ports
Control register also used to set/reset port C bits individually

31. PPI Programming Example
; Assume address decoder designed for PPI base address 0400h
; PPI is connected to D7-D0 on CPU data bus
mov dh, 04h
mov dl, 01h
mov al, 82h
out dx, al
What does the code shown above do????

32. Control Word Example
;Assume address decoder designed for PPI base address 0400h
;PPI connected to D7-D0 on CPU data bus
mov dh, 04h ;Let dh point to base address
mov dl, 03h ;Select the control register
mov al, 82h ;Place 82h Control Word into al
out dx, al ;Write al contents to PPI
;explanation of operating mode set by this code
; D7=1 Control Word (not a bit set/reset command)
; D6D5=00 A and C7-C4 are Mode 0 (Group A)
; D4=0 A is Level Sensitive Output
; D3=0 C7-C4 are Level Sensitive Output
; D2=0 B and C3-C0 are Mode 0 (Group B)
; D1=1 B is Level Sensitive Input
; D0=0 C3-C0 are Level Sensitive Output

33. 8255 Connection to Stepper Motor

34. HW#2
Sketch the schematic diagram for a 8086 minimum system that drives 8 seven segments through a PPI.
PortA of PPI serves as the driver for the segments of a digit. (PA0=a, PA1=b,..,PA6=g, PA7=‘.’;
PortB of PPI serves as the digit selection
Develop the SCAN Program.
Input: AL (0 to 7) the digit that should be shown
This routine iscalled every 10 ms
Due Date: Sunday 15 Farvardin