1. ACiD Summer School 2002 Balsa Tutorial: - 1 Build a better life with Balsa A Hands-on Tutorial Session Andrew Bardsley John Bainbridge Amulet Group, Department of Computer Science, University of Manchester, UK

2. ACiD Summer School 2002 Balsa Tutorial: - 2 Balsa Tutorials n Async 2000 (Eilat) Concentrated on language aspects Xilinx implementation of calculator n Async 2002 (Manchester) Larger exercise (SSEM) Standard cell implementations n This tutorial Language and Handshake Circuits Much larger exercise (Spamulet0) Buy the book - ISBN 0-792-37613-7

3. ACiD Summer School 2002 Balsa Tutorial: - 3 Aims of this tutorial n To show Balsa in a large(ish) example Simulate that example Modify its description (?) n Not including: Detailed examination Handshake Circuits Synthesis to netlists Implementation details

4. ACiD Summer School 2002 Balsa Tutorial: - 4 Session Schedule n Brief overview of the Balsa system n Language introduction hands-on examples “Shift Registers”: small pipelines n Either: Modify a processor description (add new instructions and simulate) Read some Balsa examples and try a simpler example (Rotate Right)

5. ACiD Summer School 2002 Balsa Tutorial: - 5 The Balsa Team Doug Edwards Team Leader Luis Plana Dual Rail Back-end Andrew Bardsley Chief Architect/Implementer Will Toms 1-of-4 Back-end Lilian Janin balsa-mgr/LARD

6. ACiD Summer School 2002 Balsa Tutorial: - 6 Balsa Requirements n Freely available ftp://ftp.cs.man.ac.uk/pub/amulet/balsa/ http://www.cs.man.ac.uk/amulet/ not all back-ends available n OS requirements: Linux Sun Solaris 7-8 (today’s platform) MacOS X (+ X11R6 …)

7. ACiD Summer School 2002 Balsa Tutorial: - 7

8. ACiD Summer School 2002 Balsa Tutorial: - 8 Front End

9. ACiD Summer School 2002 Balsa Tutorial: - 9

10. ACiD Summer School 2002 Balsa Tutorial: - 10 Compass DA Route

11. ACiD Summer School 2002 Balsa Tutorial: - 11

12. ACiD Summer School 2002 Balsa Tutorial: - 12 Xilinxroute

13. ACiD Summer School 2002 Balsa Tutorial: - 13 top level relies on Viewlogic Powerview

14. ACiD Summer School 2002 Balsa Tutorial: - 14Cadenceroute

15. ACiD Summer School 2002 Balsa Tutorial: - 15

16. ACiD Summer School 2002 Balsa Tutorial: - 16 Other Balsa Work n Burst-mode resynthesis Tibi Chelcea & Steve Nowick n Faster LARD/Balsa simulation Lilian Janin (x50 speed up) n Datapath compilation optimisation Andrew Bardsley n Complete Amulet implementation - SPA1 - Synthesised ARM v5T core Peter Riocreux, Luis Plana et al.

17. ACiD Summer School 2002 Balsa Tutorial: - 17 Proven Balsa Synthesis- DMA Controller for DRACO Balsa Synthesised DMA Controller

18. ACiD Summer School 2002 Balsa Tutorial: - 18 DMA Controller Layout

19. ACiD Summer School 2002 Balsa Tutorial: - 19 What is Balsa? n Language for synthesising large async circuits & systems n CSP/OCCAM background n Tangram-like based on Tangram compilation function compiles to a small, parameterisable, set of handshake components origins: ESPRIT 6143 EXACT project

20. ACiD Summer School 2002 Balsa Tutorial: - 20 Handshake circuits – 1 n Components communicate along handshake channels n Channels connect to ports on components n Ports have: Type Direction Sense name

21. ACiD Summer School 2002 Balsa Tutorial: - 21 Handshake Circuits – 2 n Port type determines the number of data wires no data wires = control only port! n Port direction is input, output or control only (called sync) n Port sense Active: initiate transfers (source the req) Passive: respond to requests (… the ack)

22. ACiD Summer School 2002 Balsa Tutorial: - 22 Balsa Language Features n Data types based on sequence of bits Arrays and records are bit-based Element extraction is by array slicing Strict data typing n Structural iteration n Arrayed channels n Parameterised, recursively expanded procedures

23. ACiD Summer School 2002 Balsa Tutorial: - 23 Balsa Language Features n Enclosed selection semantics Allows passive ported circuits Allows push (micropipeline-style) circuits Allows unbuffered (latch-free) circuits

24. ACiD Summer School 2002 Balsa Tutorial: - 24 Example: Single Place Buffer import [balsa.types.basic] type word is 16 bits procedure buffer (input i : word; output o : word) is variable x : word begin loop i -> x ;-- Input communication o <- x-- Output communication end

25. ACiD Summer School 2002 Balsa Tutorial: - 25 Example: Single Place Buffer import [balsa.types.basic] type word is 16 bits procedure buffer (input i : word; output o : word) is variable x : word begin loop i -> x ;-- Input communication o <- x-- Output communication end library mechanism type declaration channel declarations procedure definition implies latch repeat forever output local variable x to output channel read input channel into local variable x sequential operation

26. ACiD Summer School 2002 Balsa Tutorial: - 26 Buffer Handshake Circuit Single-place buffer  # x T ; T io activation channel repeater sequencer variable transferrer

27. ACiD Summer School 2002 Balsa Tutorial: - 27 # Buffer Handshake Circuit Single-place buffer Repeater is activated  x T ; T io

28. ACiD Summer School 2002 Balsa Tutorial: - 28 ; # Buffer Handshake Circuit Single-place buffer Sequencer handshakes to left transferrer  x TT io

29. ACiD Summer School 2002 Balsa Tutorial: - 29 ; # Buffer Handshake Circuit Single-place buffer Transferrer requests data from environment  x TT io

30. ACiD Summer School 2002 Balsa Tutorial: - 30 x ; # Buffer Handshake Circuit Single-place buffer Data transferred to variable x  TT io

31. ACiD Summer School 2002 Balsa Tutorial: - 31 x ; # Buffer Handshake Circuit Single-place buffer Variable handshake completes  TT io

32. ACiD Summer School 2002 Balsa Tutorial: - 32 x ; # Buffer Handshake Circuit Single-place buffer Transferrer handshake completes to environment  TT io

33. ACiD Summer School 2002 Balsa Tutorial: - 33 x ; # Buffer Handshake Circuit Single-place buffer Transferrer handshake completes  TT io

34. ACiD Summer School 2002 Balsa Tutorial: - 34 x ; # Buffer Handshake Circuit Single-place buffer Sequencer handshakes to right transferrer  TT io

35. ACiD Summer School 2002 Balsa Tutorial: - 35 x ; # Buffer Handshake Circuit Single-place buffer Transferrer reads variable  TT io

36. ACiD Summer School 2002 Balsa Tutorial: - 36 x ; # Buffer Handshake Circuit Single-place buffer Transferrer outputs to environment  TT io

37. ACiD Summer School 2002 Balsa Tutorial: - 37 x ; # Buffer Handshake Circuit Single-place buffer Sequencer initiated handshakes complete  TT io

38. ACiD Summer School 2002 Balsa Tutorial: - 38 x ; # Buffer Handshake Circuit Single-place buffer Sequencer completes its activation handshake  TT io

39. ACiD Summer School 2002 Balsa Tutorial: - 39 Buffer Handshake Circuit Single-place buffer Repeater initiates another transfer, repeat x ; #  TT io

40. ACiD Summer School 2002 Balsa Tutorial: - 40 Example Handshake Component n Handshake definition of repeater (Loop) Loop (a ,b ) = (a  : #[b ]) = (a   : #[b  ;b  ]) = (a r   : #[b r  ; b a  ; b r  ; b a  ]) b a b r a r a a

41. ACiD Summer School 2002 Balsa Tutorial: - 41 Example Handshake Component n Case component (single-rail) data “n” bits wide true/complement lines: dual-rail expansion 1 hot encoding

42. ACiD Summer School 2002 Balsa Tutorial: - 42 Compilation Tools n balsa-c compiles Balsa programs to Breeze includes other Breeze definition files –Breeze is a handshake -circuit netlist format –acts as a library format for within Balsa n balsa-netlist produces an appropriate netlist from a compiled Balsa program –technology specific options

43. ACiD Summer School 2002 Balsa Tutorial: - 43 Simulation Tools n breeze2lard produces a LARD simulation file n various LARD utilities mainly hidden within the Makefile by balsa-md

44. ACiD Summer School 2002 Balsa Tutorial: - 44 Utilitity Tools n breeze2ps creates a PostScript HC graph n breeze-cost enumerates the handshake circuits used and gives an approximate area cost n balsa-md automatic Makefile maker n balsa-mgr GUI interface to balsa-md

45. ACiD Summer School 2002 Balsa Tutorial: - 45 Exercise: Single Stage Shift Register Objective: introduction to balsa-mgr cd ~/Balsa/shift-reg balsa-mgr & create new project: Project -> New add SRA1.balsa to project

46. ACiD Summer School 2002 Balsa Tutorial: - 46 create new project Creating a Project

47. ACiD Summer School 2002 Balsa Tutorial: - 47 set name Set Project Name

48. ACiD Summer School 2002 Balsa Tutorial: - 48 Add Files Adding Files

49. ACiD Summer School 2002 Balsa Tutorial: - 49 pick file(s) Choosing Files

50. ACiD Summer School 2002 Balsa Tutorial: - 50 File list pane edit pane usual icons Project Window

51. ACiD Summer School 2002 Balsa Tutorial: - 51 Project Manager n tool-tip help pop-ups for icons editor icon opens the editor defined in: Project -> Environment dialogue syntax modes for xemacs, elvis, nedit n right-mouse clicking on panes brings up context sensitive menus n Browse the various menus (& pop-ups)

52. ACiD Summer School 2002 Balsa Tutorial: - 52 Single Stage Shift-Register -- Single Stage Shift Register SRA1.balsa import [balsa.types.basic] procedure SRA1 (input i : byte ; output o : byte) is variable x : byte begin loop o <- x ; i -> x end read before write

53. ACiD Summer School 2002 Balsa Tutorial: - 53 Examining the Handshake Circuits n Switch to Makefile pane in balsa-mgr n list handshake circuits & their area cost click on cost run button n view handshake circuit graph click on SRA1.ps view button

54. ACiD Summer School 2002 Balsa Tutorial: - 54 Viewing Cost click on tab

55. ACiD Summer School 2002 Balsa Tutorial: - 55 make commands identifies output pane list of HCs total cost Execution Window standard error pane standard out pane

56. ACiD Summer School 2002 Balsa Tutorial: - 56 Making Handshake Circuit Graph

57. ACiD Summer School 2002 Balsa Tutorial: - 57 repeater sequencer transferrers register internal channel names I/O ports

58. ACiD Summer School 2002 Balsa Tutorial: - 58 Exercise: n-place Shift Register Objective: illustration of composition, structural iteration and simulation. n specify an 8-place shift register add SRA8. balsa to project ensure SRA8. balsa is selected click on breeze compile button in Makefile pane select add test fixture from right-click pop- up See KvB: “Handshake Circuits”

59. ACiD Summer School 2002 Balsa Tutorial: - 59 Adding SRA8

60. ACiD Summer School 2002 Balsa Tutorial: - 60 SRA8 Code -- Multistage Shift Register SRA8.balsa import [balsa.types.basic] import [SRA1] procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : byte begin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1.. n-2 then SRA1 (c[j], c[j+1]) end

61. ACiD Summer School 2002 Balsa Tutorial: - 61 SRA8 Code -- Multistage Shift Register SRA8.balsa import [balsa.types.basic] import [SRA1] procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : byte begin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1.. n-2 then SRA1 (c[j], c[j+1]) end define a constant internal channel array parallelcomposition structuraliteration

62. ACiD Summer School 2002 Balsa Tutorial: - 62 Structure of Circuit SRA8SRA8SRA8 SRA8 …. channel i channel o channel c[1] channel c[n-1] channel c[2] channel c[n-2]

63. ACiD Summer School 2002 Balsa Tutorial: - 63 SRA8 Code -- Multistage Shift Register SRA8.balsa import [balsa.types.basic] import [SRA1] procedure SRA8 (input i : byte; output o : byte) is constant n = 8 array 1..n-1 of channel c : byte begin SRA1 (i, c[1]) || SRA1 (c[n-1], o) || for || j in 1.. n-2 then SRA1 (c[j], c[j+1]) end

64. ACiD Summer School 2002 Balsa Tutorial: - 64 Exercise: Hierarchical vs Flattened views n Check the cost of SRA8 and view the handshake circuit n Change to flattened compilation Project -> Project Options -> Flattened Compilation n Recheck the cost of SRA8 and view the handshake circuit again Flattened compilation gives “true” cost

65. ACiD Summer School 2002 Balsa Tutorial: - 65 AddingTest Fixture right click pop-up

66. ACiD Summer School 2002 Balsa Tutorial: - 66 Test Options Pane set input filename to: data

67. ACiD Summer School 2002 Balsa Tutorial: - 67 Running LARD Simulations text-onlysimulation channel-viewersimulation

68. ACiD Summer School 2002 Balsa Tutorial: - 68 Simulation Results (Text) empty values read then input data

69. ACiD Summer School 2002 Balsa Tutorial: - 69 Lard Channel Viewer -1

70. ACiD Summer School 2002 Balsa Tutorial: - 70 Lard Channel Viewer -2 input & output channels internalchannels incompletehandshakes red = request green = ack data values on channels zoom buttons

71. ACiD Summer School 2002 Balsa Tutorial: - 71 Improved Shift-Register Stage n After 1st output last stage is ready for an input: it is vacant The vacancy propagates backwards towards the input stage n Can not input a new value until vacancy reaches input stage poor throughput n Modify SRA1 to include an input and output register

72. ACiD Summer School 2002 Balsa Tutorial: - 72 Improved Shift-Register Stage Input channel i to reg x in parallel with outputting y to channel o from reg y Then assign y to x Register assignment is: y := x i o x SRC1 y

73. ACiD Summer School 2002 Balsa Tutorial: - 73 Exercise: Language Level Trade-offs n Write your own SRC1 and SRC8 copy SRA1.balsa to SRC1.balsa and edit n Compare the cost of SRC8 with SRA8 (must use flattened compilation) n Compare the behaviours of SRC8 and SRA8

74. ACiD Summer School 2002 Balsa Tutorial: - 74 Wagging Shift Register: SRW8 SRD1: demux i to o1, o2 alternately SRE1: mux i1, i2 into o alternately n Middle SR can be either type A or C SRA/C3 SRA/C3 x y x y io o1 o2i1i2 SRD1SRE1

75. ACiD Summer School 2002 Balsa Tutorial: - 75 Exercise: Build a Wagging Shift Register n SRD1 read channel i into register x while writing register y to channel o1 read channel i into register y while writing register x to channel o2 repeat n Middle Registers compose 3 type A or type C register stages in each half

76. ACiD Summer School 2002 Balsa Tutorial: - 76 Answers: SRD1 -- Single Stage Shift Register: SRD1.balsa -- DeMuxes data stream for Wagging Shift Register import [balsa.types.basic] procedure SRD1 (input i : byte; output o1, o2 : byte) is variable x, y : byte begin loop o1 y; o2 x end

77. ACiD Summer School 2002 Balsa Tutorial: - 77 Answers: SRE1 -- Single Stage Shift Register: SRE1.balsa -- Muxes data streams for Wagging Shift Register import [balsa.types.basic] procedure SRE1 (input i1, i2 : byte; output o : byte) is variable x, y : byte begin loop o y; o x end

78. ACiD Summer School 2002 Balsa Tutorial: - 78 Answers: SRW8 -- multi-Stage Wagging Shift Register SRW8.balsa import [balsa.types.basic] import [SRD1] import [SRE1] import [SRC1] procedure SRW8 (input i : byte; output o : byte) is constant n = 8 -- n must be even array 1.. n/2 of channel c1, c2 : byte begin SRD1 (i, c1[1], c2[1]) || SRE1 (c1[n/2], c2[n/2], o) || for || j in 1.. n/2 -1 then SRC1 (c1[j], c1[j+1]) || SRC1 (c2[j], c2[j+1]) end

79. ACiD Summer School 2002 Balsa Tutorial: - 79 Spamulet0 - Prototype for SPA1 n Subset of ARM instruction set n ALU ops, LDR/STR, Branch, Branch with link (procedure call) implemented Sequential, register based design, DoThis (); DoThat () n Your task is to add to this description n Spamulet0 lacks LDM/STM, MUL, SWI, Coprocessor I/F, Pipelining, Exceptions, Operating modes

80. ACiD Summer School 2002 Balsa Tutorial: - 80 The Project File cd ~/Balsa/spamulet0 n 4 Balsa files, LARD test harness types.balsa - type and instruction format records alu.balsa - ALU with CC handling shift.balsa - parameterised shifter spamulet.balsa - top-level, fetch-decode- execute loop test-spamulet.l - LARD test harness

81. ACiD Summer School 2002 Balsa Tutorial: - 81 Simulation Framework n LARD test harness provides simulated memory loaded from raw memory dump files Small number of provided examples: hello.s, multiply.s, helloc.c n Memory dumps generated from: Assembler:.s  spamulet-asm .raw C:.c  spamulet-cc .s

82. ACiD Summer School 2002 Balsa Tutorial: - 82 LDM/STM - Load/Store Multiple n Load and store any of the registers as a block - including the PC! n Commonly used for function arguments, entry register saves and return ldmdir R base ! opt, {R i, R j, …} stmdir R base ! opt, {R i, R j …} n Registers always appear in memory in the same order with R0 at lowest address, R15 at highest

83. ACiD Summer School 2002 Balsa Tutorial: - 83 LDM/STM Directions dir is one of: ib - increment before db - decrement before ia - increment after da - decrement after n Problems include loading PC last and avoiding overwriting the base register

84. ACiD Summer School 2002 Balsa Tutorial: - 84 LDM/STM Directions 2 n LDM/STM can also be used with “stack addressing” fa - full ascending (ldmda, stmib) fd - full descending (ldmia, stmdb) ea - empty ascending (ldmdb, stmia) ed - empty descending (ldmib, stmda) n The C compiler generated LDM/STMs with the stack addressing names

85. ACiD Summer School 2002 Balsa Tutorial: - 85 Instruction Encoding

86. ACiD Summer School 2002 Balsa Tutorial: - 86 Instruction Encoding – 2 Look at instLdmStm in types.balsa Use: (ir as instLdmStm) to decode instructions e.g. (ir as instLdmStm).options.L is the load(1)/store(0) select bit Option bits very similar to LDR and STR instructions, read spamulet.balsa

87. ACiD Summer School 2002 Balsa Tutorial: - 87 Implementation Strategies Edit spamulet.balsa Use a while loop and a variable to iterate through the register select bits ((inst as instLdmStm).regs) Perform memory access using MemoryRead and MemoryWrite n Don’t worry about PC or overwriting the base register yet

88. ACiD Summer School 2002 Balsa Tutorial: - 88 Some Important Information InstructionL bitP bitU bit ldmda/ldmfa100 ldmia/ldmfd101 ldmdb/ldmea110 ldmib/ldmed111 stmda/stmed000 stmia/stmea001 stmdb/stmfd010 stmib/stmfa011

89. ACiD Summer School 2002 Balsa Tutorial: - 89 Some Important Information 2 n W bit specifies whether the base register is to be written back (W=1) or keep its pre-LDM/STM value (W=0) n The “!” in the mnemonic selects writeback n Ignore the S bit - it’s used for processor mode changes (e.g. ISR returns)

90. ACiD Summer School 2002 Balsa Tutorial: - 90 Some Important Information 3 To help with debugging, Balsa has the print command n Prints simulation values in LARD n Example: b <- v1; print “Hello”; b <- v2 print “v1=“, v1, “v2=“, v2 Enjoy

91. ACiD Summer School 2002 Balsa Tutorial: - 91 Additional Exercises n A choice of advanced design exercises: A general shifter A bit population counter n Language Summary in handout + code listings

92. ACiD Summer School 2002 Balsa Tutorial: - 92 A Balsa Shifter n General shifters required for processors n Write a description for a rotate right function solution in ror/solution n Alternatively extend the standard solution to other shift functions

93. ACiD Summer School 2002 Balsa Tutorial: - 93 Structure of a ROR shifter a local procedure

94. ACiD Summer School 2002 Balsa Tutorial: - 94 Bit Population Counter n Counting the number of bits that are set to ‘1’ is necessary for ARM’s LDM/STM instructions n Write description for such a unit solution in popcount/solution

95. ACiD Summer School 2002 Balsa Tutorial: - 95 Bit Population Counter

96. ACiD Summer School 2002 Balsa Tutorial: - 96 Login and Account Setup Login with tpacidXX … Make sure this is your allocated group account name, not just tpacid02 > /usr/openwin/bin/openwin In a shell window > bash > rmdir balsa > gtar xzf /softs/balsa/examples.tar.gz