1. FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison, Part 1

2. Fundamentals of FPGA Design 1 day Designing for Performance 2 day s Advanced FPGA Implementation 2 days Intro to VHDL or Intro to Verilog 3 days FPGA and ASIC Technology Comparison FPGA vs. ASIC Design Flow ASIC to FPGA Coding Conversion Virtex-5 Coding Techniques Spartan-3 Coding Techniques CurriculumPath for ASIC Design Minimum: 6 months design experience FPGA and ASIC Technology Comparison

3. Welcome If you are an experienced ASIC designer transitioning to FPGAs, this course will help you reduce your learning curve by leveraging your ASIC experience Careful attention to how FPGAs are different than ASICs will help you create a fast and reliable FPGA design

4. Describe the differences between ASIC and FPGA architectures Explain the features of Xilinx FPGA architecture Benefit from the Xilinx dedicated resources After completing this module, you will able to:

5. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 5 © 2009 Xilinx, Inc. All Rights Reserved Contrasting Architectures ASIC architecture compared to the Xilinx FPGA architecture Gates versus LUTs Delays Performance Fundamental part selection considerations Cost Size Performance Volume Analog circuitry Time to market Reprogrammability

6. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 6 © 2009 Xilinx, Inc. All Rights Reserved Standard Cell Advantages Lowest price for high-volume production (greater than 200K per year) Fastest clock frequency (performance) Unlimited size Integrated analog functions Custom ASICs Low power Disadvantages Highest non-recurring engineering costs Longest design cycle Limited vendor IP with high cost High cost for engineering change orders

7. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 7 © 2009 Xilinx, Inc. All Rights Reserved Embedded Array Advantages Low price for medium-volume to high-volume production Performance only slightly slower than a standard cell 50+ million gates Custom macro support More flexibility than an FPGA Low power Disadvantages High non-recurring engineering costs Design cycle longer than an FPGA Vendor IP has high cost Generally digital only

8. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 8 © 2009 Xilinx, Inc. All Rights Reserved Xilinx FPGAs Field-Programmable Gate Arrays Advantages Lowest cost for low-volume to medium- volume production No non-recurring engineering costs Standard product Fastest time to market Xilinx has extensive library of IP Inexpensive compared to ASIC vendors Ability to make bug fixes quickly and inexpensively Disadvantages Slower performance Size limited to ~25 million system gates Digital only

9. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 9 © 2009 Xilinx, Inc. All Rights Reserved Field-Programmable Gate Arrays Xilinx FPGAs are made using SRAM Today’s FPGAs use 65-nm copper CMOS process Potential to accommodate 25M system gates Includes RAM and logic gates Performance up to 550 MHz Integrated synthesis, simulation, and place & route tools PC and UNIX Inexpensive: $2500 or less for the ISE Design Suite Use of third-party tools will increase costs Free ISE WebPACK is available

10. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 10 © 2009 Xilinx, Inc. All Rights Reserved Configuration Introduction When does configuration happen? On power up On demand Why do FPGAs need to be configured? FPGA configuration memory is volatile Configuration data is stored in a PROM or other external data source What do you need to know about FPGA configuration? What happens during configuration How to set up various configuration modes and daisy chains

11. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 11 © 2009 Xilinx, Inc. All Rights Reserved Configuration Cost of ownership is reduced with the ability to reconfigure the hardware—extending the life of the product Reduces the costly physical deployment of repair technicians Extends the life of the product – Upgrades – Bug fixes – Adding additional functionality – Faster time to market – Partial reconfiguration

12. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 12 © 2009 Xilinx, Inc. All Rights Reserved FPGA FPGA Configuration Methods Xilinx Cables : JTAG Slave Serial Slave SelectMAP Microprocessor : JTAG Slave Serial Slave SelectMAP Xilinx PROMs : Slave/Master Serial Slave/Master SelectMAP Commodity Flash : Slave SelectMAP SPI* BPI* *SPI and BPI support is available in the newer Virtex™-5 and Spartan™-3E families

14. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 14 © 2009 Xilinx, Inc. All Rights Reserved Five Primary Elements Routing Xilinx FPGAs Dedicated blocks Input and output blocks Configurable logic blocks * Clocking Resources

15. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 15 © 2009 Xilinx, Inc. All Rights Reserved Logic Cells Logic cells include Combinatorial logic, arithmetic logic, and a register Combinatorial logic is implemented using Look-Up Tables (LUTs) Register functions can include latches, JK, SR, D, and T-type flip-flops Arithmetic logic is a dedicated carry chain for implementing fast arithmetic operations Carry Chain LUT Carry in Carry out DQ S/R

16. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 16 © 2009 Xilinx, Inc. All Rights Reserved Combinatorial Logic LUT LUTs function as a ROM Combinatorial Logic Z They generate the output value… for a given set of inputs A B C D F E 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 0 1 1... 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 0 0 0 1 1 1 1 1 ABCDEFZ 0 0 0 1 0 1 Constant delay through a LUT Limited by the number of inputs and outputs, not by complexity

17. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 17 © 2009 Xilinx, Inc. All Rights Reserved Wide Input Functions For wider input functions, LUTs can be combined using a multiplexer LUT These muxes are dedicated, so they are fast MUX

18. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 18 © 2009 Xilinx, Inc. All Rights Reserved LUT-Based Memory Can store 64 bits of memory as either a RAM or a ROM Fundamentally, the LUT is a ROM Can become RAM with activation of configuration write strobe Combine multiple LUTs for larger memories—larger in both in depth and width 128 x 8 is not uncommon 6-input LUT contains two 5-input LUTs, which adds more flexibility LUT

19. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 19 © 2009 Xilinx, Inc. All Rights Reserved Carry Logic The carry logic chain is dedicated logic that computes high-speed arithmetic logic functions The carry chain generally consists of a multiplexer and an XOR gate The LUT computes the multiplexer selector The multiplexer determines the carry-out The XOR gate computes the addition

21. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 21 © 2009 Xilinx, Inc. All Rights Reserved Memory Blocks Support single- and dual-port synchronous operations In dual-port mode, these RAM blocks support fully independent ports for both reading and writing Each RAM block can be configured for 36 kb Can be used as 2 independent 18-kb RAMs Dedicated cascade logic allows 2 RAM blocks to be configured as 72 kb Blocks of memory are generally spread out across the die Dedicated FIFO logic enables each RAM to be configured as a FIFO

22. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 22 © 2009 Xilinx, Inc. All Rights Reserved Port A: 8 bits Port B: 32 bits ConfigurationDepthData BitsParity Bits 32k x 132 kb10 16k x 216 kb20 8k x 48 kb40 4k x 94 kb81 2k x 182 kb162 1k x 361 kb324 Block RAM Configurations Configurations available on each port IN 8 bit OUT 32 bit Independent configurations on ports A and B, read and write Supports data-width conversion, including parity bits

23. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 23 © 2009 Xilinx, Inc. All Rights Reserved IOB Element Input path Two DDR registers Output path Two DDR registers Two 3-state enable DDR registers Each path can be combinatorial or registered Separate clocks and clock enables for I and O Set and reset signals are shared

24. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 24 © 2009 Xilinx, Inc. All Rights Reserved IOB Element Default I/O standard varies by family Fast and slow slew rate Programmable drive strength Other I/O standards Built in SERDES functionality ISERDES divides input data by up to 10 OSERDES multiplies output data by up to 10

25. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 25 © 2009 Xilinx, Inc. All Rights Reserved DSP Slice 25x18 Multiply ALU Mode Pattern Detection Independent C input Dedicated A Cascading

26. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 26 © 2009 Xilinx, Inc. All Rights Reserved Routing A combination of programmable and dedicated routing lines Dedicated routing Global clocks with predefined clock tree Regional clocks and IO clocks Global low-skew routing resources for other high-fanout signals Carry chain routing Dedicated routing among other dedicated resources General interconnect Routing of local signals between CLBs and IOBs

27. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 27 © 2009 Xilinx, Inc. All Rights Reserved Clock Management Dedicated clock trees are pre-optimized clock networks that balance the skew and minimize delay Virtex-5 FPGA has 32 separate clock networks Spartan  -3 FPGA has 8 separate clock networks Each can be configured for a built-in clock enable (BUFGCE) or switching clock sources (BUFGMUX) Local clock routing includes regional (BUFR) and SERDES (BUFIO)

28. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 28 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 28 © 2009 Xilinx, Inc. All Rights Reserved Clock Management PLL Digital Clock Manager (DCM) consists of… Digital Delay Locked Loop (DLL) Digital Frequency Synthesis (DFS) Digital Phase Shifter (DPS) CMT

29. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 29 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 29 © 2009 Xilinx, Inc. All Rights Reserved I/O Translators Programmable input and output thresholds Supported standards include LVCMOS (several classes), LVPECL, HSTL (several classes), SSTL (several classes), PCI, PCI-X, LVDS (several classes), GTL, GTL+, and HyperTransport™ (LDT) technology - Supported standards vary, check your data sheet Different I/O standards require a separate input and output reference voltage for each bank supporting a separate I/O standard Generally, each bank can support several standards, as long as they share the same vref (input) or vcco (output)

30. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 30 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 30 © 2009 Xilinx, Inc. All Rights Reserved Dedicated and Special Resources Clock management (CMT) DCM and PLL Dedicated clock trees (not shown) Test logic Built-in JTAG I/O translators Supporting many different thresholds Other resources Dual-Data Rate (DDR) registers in IOB SERDES resources Dedicated Cores Block RAM DSP Slices Gigabit transceivers, MGTs (all devices) Tri-mode Ethernet MAC (all devices) PCI Express ® core (all devices) Additional FXT Cores PowerPC ® 440 processors (not shown) Faster GTX transceiver (not shown)

31. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 31 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 31 © 2009 Xilinx, Inc. All Rights Reserved Other Resources Embedded processor cores 32-bit PowerPC 440 processor core (hard) MicroBlaze  processor core (soft) Digitally controlled termination resistance (DCI)

33. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 33 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 33 © 2009 Xilinx, Inc. All Rights Reserved FPGA flexibility Reconfigurable logic Time to market Lowest “cost of change” Xilinx combinatorial resources use flexible LUTs Xilinx slices also contain registers, carry logic, clocking resources, and dedicated muxes to improve the performance for all applications Xilinx FPGAs have dedicated resources for DSP, RAM, PCI, EMAC, and I/O that make these critical paths equivalent to a custom ASIC Summary

34. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 34 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 34 © 2009 Xilinx, Inc. All Rights Reserved Where Can I Learn More? Xilinx online documents www.support.xilinx.com Software manuals Data sheets Application notes User guides Xilinx Training www.xilinx.com/training Xilinx tools and architecture courses Hardware description language courses Free training videos

35. © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 35 © 2007 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison - 35 © 2009 Xilinx, Inc. All Rights Reserved Xilinx is disclosing this Document and Intellectual Propery (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED “AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (“High-Risk Applications”). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. © 2009 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. Trademark Information