1. A Non-Coherent Multi-Band IR-UWB HDR Transceiver based on Energy Detection Mohamad Mroué, Sylvain Haese, Ghaïs El-Zein, Stéphane Mallegol and Stéphane Paquelet 17th IEEE International Conference on Electronics, Circuits and Systems December 15 th, 2010 Athens, Greece

2. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 1 Presentation progress 1. MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) 2. Analog CMOS Pulse Energy Detector (Architecture and Performance) 3. Conclusion and Prospects

3. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 2 Presentation progress 1. MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) 2. Analog CMOS Pulse Energy Detector (Architecture and Performance) 3. Conclusion and Prospects

4. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 3 Impulse radio based solution duplicated on multiple sub-bands Impulse radio based solution duplicated on multiple sub-bands Asynchronous treatment at reception based on energy detection –Amplitude modulation: On-Off Keying (OOK) –Non-coherent demodulation: energetic threshold comparison To avoid inter-symbol interference: the pulse repetition period T r must be greater than the channel delay spread T d Extension to multiple bands: to increase the system capacity … 1 1 0 1 … 1 011 TrTr TdTd Pulse generator OOK modulation Band-pass filter Pulse detector ADC Channel (S. Paquelet et al., in joint UWBST IWUWBS, 2004) Principles of the proposed system High data rate transmission with impulse radio ?

5. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 4 Transmitter architecture: filter bank implementation Transmitter architecture: filter bank implementation 3.1GHz10.6GHz 3.1GHz10.6GHz 1 1 0 0 0 1 Receiver architecture: pulse detector on each sub-band Receiver architecture: pulse detector on each sub-band 3.1GHz10.6GHz 3.1GHz10.6GHz 3.1GHz 10.6GHz 1 1 0 0 0 1 3.1GHz10.6GHz UWB HDR transceiver architecture Measured transmission responses versus frequency for a 3.1-5.2 GHz octoplexer. (De)multiplexer involved in the MB- OOK UWB transceiver (De)multiplexer involved in the MB- OOK UWB transceiver –No power division effect  In-band insertion loss < 4 dB –No external bias (Only passive devices) –Identical (de)multiplexer for Tx and Rx Advantages of the proposed architecture: Advantages of the proposed architecture: –Relaxed hardware constraints: Only coarse synchronization is needed Energy based processing –Flexibility of the multi-band architecture: Scalable data rate / power control Radio resource management n16 to 24 BiBi 250 to 500 MHz TiTi 10 to 100 ns TrTr > 25 ns Throughput (3 meters) > 600 Mbps

6. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 5 UWB HDR transceiver architecture Transceiver’s components Transceiver’s components –Commercial monocycle pulse generator Peak-to-peak amplitude into 50 Ω load: 3.29 V Duration: 184 ps, center frequency: 5 GHz –Quadriplexer (3.1-4.2 GHz) (De)multiplexer only based on filters Identical (de)multiplexer for Tx and Rx No external bias (Only passive devices) No power division effect  No need of signal amplification (In-band insertion loss < 3 dB) Mechanical etching process using low-cost organic substrate (RO3010) –Amplification stages Total amplification level of 42 dB –UWB antennas Conical monopole (Omni-directional) Horn antenna (Directional with half power beamwidth > 50° in the 3.1-4.2 GHz)

7. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 6 Measurement results in LOS and NLOS configurations Directional Antennas Omni-directional Antennas Configuration (Tx to Rx) Omni. to Omni. Omni. to Direct. Direct. to Direct. 3-dB Bandwith250 MHz Number of sub-bands24 Range (m)131313 Average delay spread (ns) 17.234.09.616.88.1511.2 Pulse repetition period (ns) 204010201015 Data rate (Gbps)1.20.62.41.22.41.6

8. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 7 Presentation progress 1. MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) 2. Analog CMOS Pulse Energy Detector (Architecture and Performance) 3. Conclusion and Prospects

9. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 8 Specifications: Specifications: Operation with large bandwidth (3.1-10.6 GHz) –Input detector bandwidth ~ 500 MHz Low mass fabrication cost Low power consumption and low complexity –The circuit must provide the pulse detection on each sub-band CMOS technology Implementation study of the detector

10. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 9 Squarer based on two MOSFETs Squarer based on two MOSFETs –When biased with zero drain to source voltage in the triode region –The circuit is driven by balanced signals –Output current: –Condition : M1 and M2 must perfectly be matched (K, a1, a2) –Avantages : Simple design No additional power consumption Principle can be applied on all CMOS IC technologies Adopted squarer circuit

11. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 10 Integrator Integrator Integrator –Current to voltage conversion and integration  directly around a capacitor –Current amplifier: Low input impedance: square law operation of the first stage High output impedance: integration and S/H stage

12. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 11 I amp I in Current amplifier Current amplifier –Input bandwidth ~ 500 MHz Useful part of the squared signal pass to the integrator unaffected –Architecture based on current mirrors Easy to implement Reduced complexity Low voltage and low power consumption Integrator Integrator –Output capacitor Current to voltage conversion Signal integration Integrator

13. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 12 Adopted architecture: open loop S/H circuit Adopted architecture: open loop S/H circuit –Charge injection effects  Sampling errors Charge injection compensation: –CMOS switch –Minimum-geometry switches –Large capacitor –Switch architecture Reset switch: low ON resistance r ON –Short discharge time for the hold capacitor Other switches: minimum (W,L) – reduce the charge injection effects –Output stage Unity gain output buffer –High input impedance Sample and hold circuit

14. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 13 Noise performance Noise performance –Noise level at the output of the detector Included detector parts: squarer, current amplifier, switch (ON state) and the hold capacitor Estimated noise level: ~ 1 % of the useful signal level Imperfection effects study Imperfection effects study –Effect of the input impedance of the current amplifier on the squarer Gain variation of the squarer as a function of the input impedance Effects of the MOS transistors’ parameters variations Effects of the MOS transistors’ parameters variations –Squarer operation: Effect on the gain of this stage The square law function of the squarer is not affected –Current amplifier operation: Current offset and gain A modification of the architecture permit to reduce the generated offset current Circuit performance

15. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 14 Time domain simulation Time domain simulation –Simulator: CADENCE Spectre –Technology : AMS 0.35 μm BiCMOS Pulse detector architecture Circuit parameters Squarer (W/L) N 40/0.35VGVG 1 V Current amplifier (W/L) N 7.2/0.35Bandwidth at 3dB563 MHz (W/L) P 70/0.35V DD = - V SS 1.8 V I bias 84.5 μAPower consumption0.6 mW Output stage I0I0 240 μABandwidth at 3dB825 MHz V DD = - V SS 1.8 VPower consumption1.6 mW

16. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 15 Pulse Energy Detector with two parallel stages for the integrator and S/H stages. Pulse Energy Detector with two parallel stages for the integrator and S/H stages. –Time domain simulation Simulator: CADENCE Spectre Technology : AMS 0.35 μm BiCMOS T r = 15 ns, T i = 13 ns, T Reset = 3 ns, T s = 8 ns Pulse detector architecture Input pulse Integration Sampling Reset 1 0 1 Transmitted code:

17. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 16 Presentation progress 1. MB IR-UWB Transceiver for HDR Applications (Modulation Principles and Architecture) 2. Analog CMOS Pulse Energy Detector (Architecture and Performance) 3. Conclusion and Prospects

18. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 17 Conclusion Conclusion –Functional tests of the communicating system in real environment –Comparison between the use of directional and Omni-directional antennas in LOS and NLOS configurations –Implementation evaluation of the proposed Multi-band IR-UWB system MB IR-UWB receiver architecture MB IR-UWB receiver architecture Conclusion and prospects Base-band: pulse energy detection Power consumption: ~ 40 mW Analog Front-End: LNA and VGA with an appropriate technology Power consumption: ~100 mW Filter bank: no additional power consumption LTCC technology (Low Temperature Co-fired Ceramic) SiP approach (System in Package) CMOS Technology

19. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 18 Thank you for your attention !

20. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 19 ITE-UWB HDR ITE-UWB HDR Principles Performances: optimal demodulation rule Energy demodulation problem for OOK (one sub - band)  two symmetric hypothesis  Objective : minimise error probability knowing  and after estimating Optimal threshold  with  Special demodulation threshold Probability densities  où S. Paquelet, L-M. Aubert et al, UWBST 2004, « An Impulse Radio Non-coherent Transceiver for High Data Rates »

21. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 20 E/N (dB) Pe Coherent - RAKE receiver:  Energy recovered on few paths whereas Quadratic integration:  Whole available energy recovered rake achieves comparable if it collects 33% to 40% of the whole available energy. Extended Notion of OFDM  orthogonal carrier orthogonal pulses  intrinsic fading resistance S. Paquelet, L-M. Aubert et al, UWBST 2004, « An Impulse Radio Non-coherent Transceiver for High Data Rates » CM: IEEE Channel Models - 2: NLOS 0-4 meters - 3: NLOS 4-10 meters - 4: Extreme NLOS multipaths * without FEC ITE-UWB HDR ITE-UWB HDR Principles Performances/Comparisons

22. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 21 Mean performance for a given received energy when considering the FCC limitations

23. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 22 Quadriplexer (3.1-4.2 GHz) Mechanical etching process Mechanical etching process Low cost organic substrate RO3010 Low cost organic substrate RO3010 –« Ceramic-filled PTFE composite » –Dielectric constant : 10.2 –Metallization thickness : 17 µm Architecture Architecture –1 Low pass filter –4 bandpass filters Based on resonators No power division effect No power division effect (S. Mallégol et al., EuRAD&EuMC, 2006) Sub- band (GHz) Central Frequency (F c, GHz) Insertion loss at F c (dB) Bandwidth at 3 dB (MHz) Bandwidth at 10 dB (MHz) 3.1-3.223.1512.68185.8308.4 3.44-3.553.4952.23199.8295.3 3.79-3.913.8342.33196.2309.4 4.13-4.254.1932.43193.3322.2 Intercept-point magnitude between adjacent sub-bands > 14 dB

24. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 23 Octoplexer (3.1-5.1 GHz) ANR BILBAO Project ANR BILBAO Project Size: 71 mm  62 mm In (S. Mallégol et al., EuRAD&EuMC, 2006)

25. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 24 Monocycle- pulse generator 3.1-5.2 GHz Octoplexer Out1 Out8 Measurements results CADENCE simulation results Non-filtered monocycle pulse Into 50  : V peak-to-peak = 3.29 V Duration = 184 ps The first 4 pulses at the outputs of the 3.1 – 5.2 GHz octoplexer (Tx) Spread of the output pulses < 6 ns (< T d ) Measurements and simulation results LNA

26. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 25 Objective: to reduce current offset level generated at the output Objective: to reduce current offset level generated at the output –Modifying the architecture of the current amplifier –Altering the positions of two p-channel and n-channel MOS transistors  Compensation of effects of MOS transistors’ parameters variations  The current offset is reduced by 4 to 5 times Modified current amplifier architecture

27. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 26 Evaluation of the current offset variation generated at the output of the current amplifier Evaluation of the current offset variation generated at the output of the current amplifier Variation of the threshold voltage V T and the transconductance factor K –Comparison between analytical and simulation results Variation effects of MOS transistors’ parameters

28. Mohamad Mroué 17 th IEEE ICECS 2010 December 15 th, 2010 27 New Monte-Carlo simulation results using CADENCE with variations on mismatch and both mismatch and process parameters New Monte-Carlo simulation results using CADENCE with variations on mismatch and both mismatch and process parameters Modified current amplifier architecture mismatchmismatch & process