1. Design, Synthesis and Test of Network on Chips
University of Tehran
Technical faculty
Electrical and Computer Engineering Faculty
Design, Synthesis and Test of Network on Chips
Presented By: Atefe Dalirsani
ASIC Course
Instructor: Dr. S. M. Fakhraei
May 2006
Class Presentation for Educational Purposes

2. Outline On-chip bus architecture problem NoC design
NoC design trade-offs and considerations
Switch block design
Performance evaluation
NoC synthesis
NoC synthesis tools
Testing NoC based systems
Reliable SoC/NoC Design

3. On-chip Bus Architecture Problems
2010: MPSoC devices, many GHz, below one volt, complex communication architectures
In today’s SoC devices, all of the IP blocks are connected by global on-chip buses but this global interconnect is increasingly dominating the delay, power, and area of integrated circuits
Traditional on-chip bus architectures are becoming a bottleneck for two reasons:[4]
bus interface in each IP block needs to be frequently modified
interconnections in each new technology generation, become more complex as they need to connect more on-chip functions with the result that cost/performance factors such as silicon area, on-chip communications speed and overall power consumption are increasingly dominated by the bus.
By 2010, according to the International Technology Roadmap for Semiconductors projections, Multiprocessor System-on-Chip (MPSoC) devices will contain billions of transistors running at many GHz, operating below one volt. In general, an MPSoC can be considered as comprising a number of processing elements (PEs) and storage elements (SEs) connected by complex communication architectures. PEs implement one or more functions using programmable components, including general-purpose processors and specialized cores, such as digital signal processor (DSP) and very long instruction word (VLIW) cores, as well as embedded hardware, such as FPGA or application-specific intellectual property (IP), analog front- end, peripheral devices and so on.
One of the key issues in the evolution of MPSoC is the nature of the on-chip communications architecture. In today’s SoC devices, all of the IP blocks are connected by global on-chip buses but this global interconnect is increasingly dominating the delay, power, and area of integrated circuits and there is a strong industry consensus that a radically new on-chip communications architecture will be needed in the future.
Traditional on-chip bus architectures are becoming a bottleneck for two reasons. First, bus architectures need to continually evolve to keep pace with the ever-increasing complexity of SoC devices, which means that the bus interface in each IP block needs to be frequently modified, which increases the time-to-market of new SoC solutions. The second is that rather than behaving like transistors and scaling down in accordance with Moore’s law, interconnections in each new technology generation, become more complex as they need to connect more on-chip functions with the result that cost/performance factors such as silicon area, on-chip communications speed and overall power consumption are increasingly dominated by the bus. In the long term, techniques such as optical intra-chip communications, in which ST has already reported world-leading R&D results, may eliminate this problem. In the medium term, new intra-chip interconnection technologies will be required to maintain the combination of price/performance/power improvements required by customers.

4. NoC Solution
NoC is a new concept that emerged from the academic world as recently as 2000 and has since been the subject of intensive academic and industrial research. Numerous innovative NoC architectures have been proposed by a variety of universities and industrial research labs, including KAIST (Korea Advanced Institute of Science and Technology), KTH (Royal Institute of Technology, Sweden), Laboratoire d’Informatique de Paris 6, MIT, Philips Research Lab, STMicroelectronics, Technion (Israel Institute of Technology), and VTT Technical Research Centre (Finland), as well as Universities such as Bologna, Manchester, San Diego, Stanford, and Tampere.
Many issues about NoC concepts as a solution for MPSoC interconnects are still open such as: the choice of the network topology, the packet and message format, the end-to-end services, the routing strategies, the flow control and the queuing management
The user expects answers in the tens of topics involved in 'real world' NoC design such as: reset, QoS, testability, application debug, timing convergence, error logging, compatibility with existing standard, etc.[3]
NoC is a new concept that emerged from the academic world as recently as 2000 and has since been the subject of intensive academic and industrial research. Numerous innovative NoC architectures have been proposed by a variety of universities and industrial research labs, including KAIST (Korea Advanced Institute of Science and Technology), KTH (Royal Institute of Technology, Sweden), Laboratoire d’Informatique de Paris 6, MIT, Philips Research Lab, STMicroelectronics, Technion (Israel Institute of Technology), and VTT Technical Research Centre (Finland), as well as Universities such as Bologna, Manchester, San Diego, Stanford, and Tampere.
However, while research to date has provided a strong agreement that the NoC concept will offer an attractive solution to the MPSoC interconnect problem, many issues are still open, including, for example, the choice of the network topology, the packet and message format, the end-to-end services, the routing strategies, the flow control and the queuing management
Academic work in the NoC area has always concentrated on a specific topic, packet based switching for example, while the user expects answers in the tens of topics involved in 'real world' NoC design. These system level topics include; reset, QoS, testability, application debug, timing convergence, error logging, compatibility with existing standard, etc. Arteris offers the first commercial solution addressing the complete range of NoC challenges.

5. NoC Design
Network-on-a-chip (NoC) paradigm is emerging as a new design methodology to meet the communication requirements of large SoCs  new trends
Various trade-offs regarding latency, throughput, reliability, energy dissipation, silicon area requirements and application’s nature characterize communication-centric interconnect fabrics
Borrow communication models and techniques from networking and parallel processing  micronetwork  energy efficiency and QoS
[1]

6. Design Trade-offs for NoCs
Throughput: the maximum load the network can physically handle  system aggregate bandwidth
Latency: the time that elapses between a message injection into the network at the source node and the end of packet reception at the destination node.
When data travels on the interconnection network, both the inter-switch wires and the logic gates in the switches toggle  energy dissipation
Additional buffer and register area, estimating wire area complexity  longest wire segments,
[2]

7. Design Considerations
Performance perspective: high throughput and low latency (such as MPSoC platforms)
VLSI perspective: interconnect architecture’s energy dissipation profile significant portion of the overall energy budget
Silicon area overhead resulting from the interconnect fabric
Processor and storage cores communicate with one another through high-performance links and intelligent switches, and communication design can be represented at a high abstraction level.
Although the design process for NoC-based systems borrows some aspects from the parallel computing
domain, it is driven by a significantly different set of constraints. From the performance perspective, high throughput and low latency are desirable characteristics of MP-SoC platforms. However, from a VLSI design perspective, the interconnect architecture’s energy dissipation profile is critical because it can represent a significant portion of the overall energy budget. Silicon area overhead resulting from the interconnect fabric is important too. The common characteristics of these kinds of architectures are that the processor and storage cores communicate with one another through high-performance links and intelligent switches, and communication design can be represented at a high abstraction level7

8. Switch Block Design Packet-based on-chip communication
Wormhole switching
Divide packets into fixed-length flow control units (flits)
I/O buffers for storing only a few flits
Minimizes the buffer space in the switches  switches are small and compact
Header flit decoding enables switches to establish the path
Subsequent flits simply follow this path in a pipeline fashion
If a flit faces a busy channel, subsequent flits must wait at their current locations
Switch design also depends on the routing scheme adopted. The two broad categories of routing are deterministic and adaptive. Deterministic routing algorithms always provide the same path between a given source and destination pair. Adaptive routing algorithms use information about routing traffic or channel status to avoid the congested or faulty part of the network. In a deterministic routing scheme, switches can be fast and compact.

9. Switch Bock Design (Cont.)
Routing scheme
Deterministic
Adaptive
[1]
Switch design also depends on the routing scheme adopted. The two broad categories of routing are deterministic and adaptive. Deterministic routing algorithms always provide the same path between a given source and destination pair. Adaptive routing algorithms use information about routing traffic or channel status to avoid the congested or faulty part of the network. In a deterministic routing scheme, switches can be fast and compact.

10. Performance Evaluation
NoC-based interconnect performance correlates strongly with the topology  regular , irregular
Regular arch. : performance level is homogeneous across the whole system  for the realization of multiprocessor communication schemes
Irregular arch. : vary widely for the different processors and storage blocks  for realizing application specific SoCs such as those in mobile-phone systems
In the case of custom-built NoC architectures, switch blocks might not be identical; their design and placement depend on the specific communication requirements

11. NoC Synthesis
NoCs have no specialized languages or formalisms for their high-level modeling
Synthesis is useful in both homogeneous and heterogeneous network architectures.
Designers can realize the network by means of components such as switches, links, and network interfaces.
NoCs have no specialized languages or formalisms for their high-level modeling. Nevertheless, structural formalisms can help designers model network topologies, and procedural languages such as SystemC and C++ can capture hardware and software behavior.
Synthesis is useful in both homogeneous and heterogeneous network architectures, but it is critical in the latter because designers must choose from, and experiment with, different topologies and parameters when searching for the best match for an application.

12. Reasons for Using NoC synthesis
Sometimes the best network architecture, protocols, and parameters for a given system application aren’t known.
There are many parameters to optimize in an on-chip network implementation.
A synthesis flow allows fast design and lets designers concentrate on system issues while leaving details to the tools
1- To find the best solution, a designer must experiment with different models having various performance, energy consumption, and layout complexity trade-offs. Eventually, it will be possible to choose the network topology, protocols, and parameters automatically or with CAD tool support. In the interim, fast, automatic generation of models that the network can simulate can help designers make informed choices.
2- CAD tools can help optimize the implemented circuitry by, for example, sizing switches and links to provide adequate QoS with minimal area overhead and energy dissipation. Fine-tuning NoCs is hard and time-consuming, especially in the case of heterogeneous fabrics and networks.
3- When coping with the challenges of communication-centric SoCs, designers must use network synthesis to close the productivity gap in
much the same way that logic synthesis has expedited semicustom design.

13. NoC Synthesis Tools NoC libraries : xPipes, xPipesLite [1]
xPipes Compiler: a network synthesis tool for xPipes [1]
Sunmap9: automatic topology selection tool [1]
Arteris: develops and markets products enabling chip designers and system architects to effectively build the on-chip communications infrastructure for chips comprised of many discrete building blocks [3]
Examples of NoC libraries include
xPipes4 and xPipesLite the latter is a simpler, faster, and synthesizable version of the former. The xPipes compiler is a network synthesis tool for
xPipes, and Sunmap9 is an automatic topology selection tool. Designers have used the libraries and tools to realize experimental gate-level
models of complex system applications.

14. xPipes Compiler
[1]

15. Arteris NoC Solution [3]

16. Sunmap – Automatic Topology Selection Tool
[1]

17. Testing NoC-based Systems
Testing functional and storage blocks and their corresponding network interfaces
Several parallel path for transmitting test data
Testing the interconnect infrastructure
Testing the switch blocks
FIFO buffer
Router logic
Testing the inter-switch wire segments
Testing the integrated system
Testing the functional and storage blocks and the interconnect infrastructure separately isn’t enough to ensure adequate test quality. Interaction between the functional and storage cores and the communication fabric must also undergo extensive functional testing, which should encompass testing the I/O functions of each processing element and the data routing functions.

18. Reliable SoC/NoC Design
Error control coding
Advantage of packetized communication is the possibly of incorporating error-control information into the transmitted data stream
Distributed error recovery mechanism
Centralized error recovery mechanism
Fault tolerant architectures
In NoC architectures, the error recovery mechanism can be distributed over multiple hops or concentrated at the end nodes. In distributed schemes, each switch has error detection or correction circuitry such that transmission of corrupted data can be stopped or corrected at the intermediate switches. In centralized mechanisms, the retransmission of corrupted data can cause a severe latency penalty, especially when the
source and destination nodes are far apart. Therefore, the trade-off related to the localization of error detection
and correction involves several figures of merit, such as latency, area, and power consumption.

19. Conclusion
Commercial designs are integrating from 10 to 100 embedded functional and storage blocks in a single SoC
Several industrial and academic research groups are striving to develop efficient communication architectures
NoC is an enabling solution for this level of integration
Major issues include the detailed design trade-offs and the performance optimization
NoC tools for design and synthesis in higher levels of abstraction

20. References
[1]: P. P. Pande et al., “Design, Synthesis and Test of Networks on chips,” IEEE design & test of computers, Sep
[2]: P.P. Pande et al., “Performance Evaluation and Design Trade-offs for Network-on-Chip Interconnect Architectures,” IEEE Trans. Computers, vol. 54, no. 8, Aug. 2005, pp
[3]:
[4]:
[5]: S. Kumar et al., “A Network on Chip Architecture and Design Methodology,” IEEE computer society annual symposium on VLSI, 2002
[6]: M.Hosseinabady et al, “A Concurrent Testing Method for NoC Switches,” DATE Conference, 2006.