1. ON LINE TEST GENERATION AND ANALYSIS R. Šeinauskas Kaunas University of Technology LITHUANIA

2. Tools n n On line test generation and analysis tools are developed under project REASON n n All tools have common frame and are accessible by conventional browser after registration

3. QUESTION n n Why tools on high level of abstraction are necessary?

4. Introduction Idea, Algorithm RTL Description Gate Level Netlist Layout Defect-Based Test Generation Defects Conventional Test Generation Fault model of gates High-Level Test Generation Description distortion model Test Generation for Algorithms Black-box fault model

5. Test Generation Tasks Conventional Test Generation Fault model of gates High-Level Test Generation Description distortion model Test Generation for Algorithms Black-box fault model Defect-Based Test Generation Defects Test generation for all possible realizations of circuit description Test generation for defects Test generation for all possible realizations of cells Test generation for all possible descriptions and all possible realizations of circuit

6. ASIC Design Flow n n In the standard ASIC design flow the designers mainly work on RT- (or higher) level descriptions. n n Nowadays logic synthesis tools automatically generate gate-level descriptions. n n However, most of the test activities (test structure insertion, test vector generation, fault coverage evaluation, etc,) are still performed on the gate- level netlists.

7. Time-to-Market n n Time-to-Market depends on the duration of the logic and layout synthesis and on the duration of the design for test and test generation. n n The design for test and test generation on the system level-level model can reduce time-to- market. n n Starting test development at the end of the design process greatly prolongs the time-to-market.

8. System-level model n n If a top-down design methodology is used, then a system-level model of the chip exists early in the design process. n n This system-level model can be used during the development of the test program. n n Thus, the test engineers can become involved with the project much earlier, and like the block designers, are given a working virtual prototype of the chip in the form of a system–level model.

9. Time-to-Market System- level model RT-level model Gate-level model Layout DFT and Test generation

10. Design complexity n n Design complexity drives the need to reuse legacy or IP ( intellectual Property) cores in Systems on a chip ( SoC). n n High Level modules of SoC are often specified in terms of their behavior only. n n SoC designs rely heavily on reusable and pre- designed cores or intellectual property ( IP) modules, whose gate-level implementation details are unavailable.

11. Test reuse n n Systems designers become system architects reusing more and more proven components and their test processes. n n Test reuse must follow the same path. n n Conventional single–at fault models associated with internal logical gates or their inter connections are not applicable for test reuse. n n Structural defect-based test involves no test reuse, as tests are usually generated after structural synthesis.

12. Reusable tests n n The implementation depends on SoC manufacturing technologies and is permanently changing in SoC lifecycle. n n Time-to-Market, reuse legacy or IP cores in Systems on a chip design drives the need to use realization-independent testing. n n How core vendors can provide reusable tests for new implementations?

13. Important questions n n Can a test based on functional fault model be effective in uncovering physical defects? n n How is its effectiveness dependent on the synthesized structure? n n These are important questions, not only for test reuse, but also due to fact that soft cores can be synthesized by different electronic design automation systems, and mapped in different cell libraries and manufacturing technologies.

14. Design Flow System- level model Gate-level model Synthesis DFT and Test generation Time-To-Market System- level model Synthesis DFT and Test generation Gate-level model Test sequences Test supplement on switch-level model Test supplement on System-level model Defect coverage analysis

15. Design Flow n n In any case fault coverage analysis on gate level model is necessary, but it is not time consuming task. n n The length of test sequences generated on system- level model can be compacted together with the fault coverage analysis. Therefore, the length of test sequences generated on system-level model is not a critical parameter.

16. On Line Tools n n User needs only Browser n n The model on programming language C n n Login name and Password will be send by e-mail