1. Cores vs. Caches CS 838 Project Matt Ramsay & Chris Feucht

2. Motivation As feature sizes push smaller, additional hardware can be placed on chipAs feature sizes push smaller, additional hardware can be placed on chip Various trade-offs resultVarious trade-offs result Among these for a CMP is how many cores and how much cache on each chipAmong these for a CMP is how many cores and how much cache on each chip Our project results suggest an optimal configuration for a 16-processor system running web-based applicationsOur project results suggest an optimal configuration for a 16-processor system running web-based applications

3. Outline MotivationMotivation Experiments PerformedExperiments Performed Simulator EnvironmentSimulator Environment ResultsResults Project ShortcomingsProject Shortcomings Future WorkFuture Work Conclusions & SummaryConclusions & Summary

4. Experiments Intended experiments not performed due to simulator limitationsIntended experiments not performed due to simulator limitations Intended experiments: Each core equivalent to.5 MB L2 cacheIntended experiments: Each core equivalent to.5 MB L2 cache Ran apache_8, oltp_2, zeus_8Ran apache_8, oltp_2, zeus_8

5. Simulator Environment All nodes include 32 KB, 2 way L1 I & D cachesAll nodes include 32 KB, 2 way L1 I & D caches Each nodes has its own L2 bank, regardless of L2 size or assoc.Each nodes has its own L2 bank, regardless of L2 size or assoc. All other ruby and opal settings left at defaultAll other ruby and opal settings left at default

6. Results - Apache

7. Results - OLTP

8. Results – Zeus

9. Project Shortcomings & Future Work Longer runs needed for convincing dataLonger runs needed for convincing data Test different number of processors/systemTest different number of processors/system Add L3 cache to memory hierarchyAdd L3 cache to memory hierarchy

10. Conclusions CPI (IPC) changes little in a 16- processor system as number of cores/chip variesCPI (IPC) changes little in a 16- processor system as number of cores/chip varies This happens despite rapid system- wide L2 cache growth with added chipsThis happens despite rapid system- wide L2 cache growth with added chips Best performance per cost is with all 16 processors on one chipBest performance per cost is with all 16 processors on one chip –Even with 2 MB total L2 –Would be helped by off-chip L3

11. Project Summary We look here! 50 miles