1. Implementing the Controller

2. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

3. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

4. Implementing the Controller  Once the state table is obtained, the controller can be implemented using one of these techniques. 1. Traditional method: With JK flip-flops  design done at gate level.  suitable for small controllers.  procedure: prepare state table, use K-maps to obtain next- state/output functions. 2. Decoder + D flip-flops  suitable for moderately large controllers.  procedure: use decoder to obtain individual states; from the state table, obtain the next-state functions by inspection.

5. Implementing the Controller 3. Multiplexers  a more structured approach to implement controller.  suitable for moderately large controllers.  three level structure: first level consists of multiplexers that determine the next state of the register; second level is a register that holds the present state; third level has a decoder to provide separate output for each controller state.

6. Implementing the Controller 4. One flip-flop per state  also known as One-Hot Spot Method of ASM synthesis.  procedure: allocate one flip-flop per state; from state table, determine the formulae to set each flip-flop; must ensure that controller is properly initialized. 5. PLA/ROM  highly regular approach.  ROM approach uses a very simple table lookup technique but suffers from large number of don’t care states.  PLA can handle don’t care states well but design method is still at gate-level.

7. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

8. Implementing Controller: With JK Flip-flops  State table obtained from ASM chart:  Corresponding state table using JK flip-flops:

9. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

10. Implementing Controller: Decoder + D Flip-flops  The flip-flop input functions can be obtained directly from the state table by inspection.  This is because for the D flip-flops, the next state = flip-flop D input.  Decoder is then used to provide signals to represent different states. D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 ? ? clock

11. Implementing Controller: Decoder + D Flip-flops  Given the state table:  We can directly determine the inputs of the D flip-flops for G 1 and G 0. DG 1 = T 1.A 2.A 3 DG 0 = T 0.S + T 1

12. Implementing Controller: Decoder + D Flip-flops  Flip-flop input functions: DG 1 = T 1.A 2.A 3 DG 0 = T 0.S + T 1  Circuit: D Q D Q 2x4 decoder T0T0 T1T1 T2T2 unused G1G1 G0G0 clock A2A2 A3A3 S

13. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

14. Implementing Controller: One Flip-flop per State  Require n flip-flops for n states; each flip-flop represents one state. (Other methods: n flip-flops for up to 2 n states.) D Q D Q T1T1 T0T0 ? ? clock ::::

15. Implementing Controller: One Flip-flop per State  Formulae for next state can be obtained directly from state table: 1. If there is only one line going into the state, then formula = input condition ANDed with the previous state. 2. If there are more than one line, then formula = Ored of all the conditions found in (1).

16. Implementing Controller: One Flip-flop per State  State table:  State diagram: T0T0 S=0A 2 =0 T1T1 S=1 A 2 =1, A 3 =0 T2T2 A 2 =1, A 3 =1  Flip-flop input functions: DT 0 = T 2 + S'.T 0 DT 1 = S.T 0 + A 2 '.T 1 + A 2.A 3 '.T 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1

17. Implementing Controller: One Flip-flop per State  Circuit diagram below. To initialize to state T 0, set flip-flop of T 0 to 1 and clear the rest to zero. DT 0 = T 2 + S'.T 0 DT 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1 D Q T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 clear preset

18. Implementing Controller: One Flip-flop per State  Alternative: Use Q' output for T 0, and input function for T 0 is complemented. To initialize, clear all flip-flops to zero. DT 0 = (T 2 + S'.T 0 )' DT 1 = S.T 0 + (A 2.A 3 )'.T 1 DT 2 = A 2.A 3.T 1 D Q T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 clear Q'

19. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

20. Implementing Controller: Multiplexers  Purpose of multiplexer is to produce an input to its corresponding flip-flop equals to the value of the next state.  The inputs of multiplexers are determined from the decision boxes and state transitions in the ASM chart.

21. Implementing Controller: Multiplexers  Example 1: Given the state table.  Reformat the state table.

22. Implementing Controller: Multiplexers  Obtain multiplexer inputs:

23. Implementing Controller: Multiplexers  Draw the circuit: T1T1 T0T0 S clock D Q D Q T2T2 A2A3A2A3 2x4 decoder G1G1 G0G0 MUX1 01230123 S 1 S 0 MUX0 01230123 S 1 S 0 0 0 0 1 Determine next state of register Hold present state

24. Implementing Controller: Multiplexers  Example 2: w 0 1 T0T0 00 T1T1 01 x 10 T3T3 11T2T2 10 y 10 y 01 z 10 z 01

25. Implementing Controller: Multiplexers T1T1 T0T0 w clock D Q D Q T3T3 yzyz 2x4 decoder G1G1 G0G0 MUX1 01230123 S 1 S 0 MUX0 01230123 S 1 S 0 y' y 0 x' 1 y z' T2T2

26. Outline  Implementing the Controller  With JK Flip-flops  Decoder + D flip-flops  One Flip-flop per State  Multiplexers  PLA/ROM

27. Implementing Controller: PLA/ROM  Similar to the design using D flip-flops and a decoder.  The only difference is PLA essentially replaces the decoder and all the gates in the inputs of the flip-flops. PLA/ROM External command Commands to architecture Present state Next state Register to represent states