1. The GANDALF Multi-Channel Time-to-Digital Converter (TDC)  GANDALF module  TDC concepts  TDC implementation in the FPGA  measurements

2. The GANDALF module June 13, 2011Sebastian Schopferer2 VME64x Interface USB 2.0 S-Link Interface to DAQ S-Link Interface to DAQ VITA 41.0 VXS Interface VITA 41.0 VXS Interface TCS Memory: 144 Mbit QDRII+, 4 Gbit DDR2 Memory: 144 Mbit QDRII+, 4 Gbit DDR2 Virtex-5 SX95T FPGA for Data Processing: 60k CLB flip-flops, 8 Mbit Block RAM, 640 DSP Slices, 500 MHz Virtex-5 SX95T FPGA for Data Processing: 60k CLB flip-flops, 8 Mbit Block RAM, 640 DSP Slices, 500 MHz mezzanine card slot 1 G eneric A dvanced N umerical D evice for A nalog and L ogic F unctions mezzanine card slot 2 Virtex-5 LX30T FPGA for Memory Control & Data Output: 20k CLB flip-flops, 1.2 Mbit Block RAM, 500 MHz Virtex-5 LX30T FPGA for Memory Control & Data Output: 20k CLB flip-flops, 1.2 Mbit Block RAM, 500 MHz

3. The GANDALF module June 13, 2011Sebastian Schopferer3 GANDALF transient recorder 16 analog inputs for A/D conversion (500 MS/s @ 12 bit) optional time-interleaved mode: 8 channels with 1000 MS/s real-time pulse shape analysis with online feature extraction (time resolution up to 10 ps) GANDALF with digital inputs / outputs 128 differential inputs or outputs module functionality is free programmable in the FPGA e.g. time-to-digital converter, scaler, mean-timer, coincidence matrix, pattern generator combinations of these functionalities are possible for cost efficient design

4. Digital Mezzanine Card (DMC) June 13, 2011Sebastian Schopferer4 buffer card to convert signal levels and protect FPGA from short circuits and ESD 2 x 32-channel VHDCI connectors 64 differential inputs (e.g. LVDS, LVPECL) or 64 differential outputs (LVDS) 1x NIM input, 2x NIM outputs jitter < 20 ps (including FPGA inputs)

5. GANDALF TDC design objectives June 13, 2011Sebastian Schopferer5 more about the GANDALF module: http://hadron.physik.uni-freiburg.de/gandalf/  128 TDC channels per board  time resolution better than 100 ps rms  leading and/or trailing edge sensitivity  multi-hit capability  10 ns double hit resolution  18 bit dynamic range  20 µs look-ahead / look-back hit buffer  programmable trigger window  dead-time free data readout

6. TDC concepts June 13, 2011Sebastian Schopferer6 Shifted Clock Sampling  equidistant delay of data signal ∆ t delay = 1/(n*f clk )  same clock signal at all flip-flops  equidistant phase shift of clock signal φ delay = 2 π /n  same data signal at all flip-flops Delayed Data Sampling sampling of data signal  TDC bin width = 1/f max ≈ 2 ns f max : 500 MHz (Virtex-5) reduce TDC bin width by: Trivial concept of TDC

7. Shifted Clock Sampling June 13, 2011Sebastian Schopferer7 bit pattern “11000000”  hit detected! time(TDC bin) = clk_counter * 8 + ‘bitswap’ position Hit 8 phase shifted TDC clocks 8 TDC flip-flops data signal check for ‘bit pattern’ ≠ “00000000” or “11111111” output register

8. Partitions June 13, 2011Sebastian Schopferer8  eight different clock domains -register outputs are not stable simultaneously -readout not possible at a single point in time  “partitions” are introduced to merge the clock domains in a two-stage process 1 2 5 6 7 3 partition 1 ‘overlap’ avoids loss of hits! partition 0 0 0 4 4 Setup & hold readout 012345670012345670

9. Implementation June 13, 2011Sebastian Schopferer9 Challenge  accuracy of TDC bin width influenced by  clock „phase error“  „routing delay“ of data signal 8 TDC- flip-flops routing resources routing of data signal to TDC flip-flops  placement is user-controlled by scripts  auto-router finds appropriate connections

10. Implementation June 13, 2011Sebastian Schopferer10 clock 0º clock 90º clock 180º clock 270º clock 0º clock 90º clock 180º clock 270º clock 45º clock 135º clock 225º clock 315º clock 45º clock 135º clock 225º clock 315º PLL 1 PLL 2 Phase-shifted clocks produced by two PLLs

11. Trigger Matching June 13, 2011Sebastian Schopferer11  time stamp measurements  select only hits within a time window around a trigger signal  trigger signal can be related to data in the past (“look-back”) or in the future (“look-ahead”)  hit data storage inside FPGA needed max. latency: 20 µs HIT FIFO depth: 1k max. latency: 20 µs HIT FIFO depth: 1k

12. TDC overview June 13, 2011Sebastian Schopferer12 TDC register (8 flip-flops) clk0clk3clk1clk4clk2clk6clk5clk7 partition 0partition 1 Hit Buffer RAM Trigger Trigger Matching Output FIFO Clock Counter Data merge 128 channelsDAQ

13. FPGA resource usage June 13, 2011Sebastian Schopferer13 average resource usage per TDC channel 1 TDC channel

14. Measurement Setup June 13, 2011Sebastian Schopferer14 Pattern Output (LVDS) TDC Input (LVDS) TCS in TDC GANDALF (input) Pattern Generator (output)  clock frequency 388.8 MHz  8 phase-shifted clocks  TDC bin width: 320 ps  clock frequency 388.8 MHz  8 phase-shifted clocks  TDC bin width: 320 ps

15. Measurements June 13, 2011Sebastian Schopferer15 not optimized : optimized : PLL1 PLL2 Differential Nonlinearity

16. Extension to 16 TDC bins June 13, 2011Sebastian Schopferer16 partition 1 partition 0 1 2 5 6 7 3 0 0 4 1 2 5 6 7 3 0 0 4 rising-edge-triggered falling-edge-triggered  clock frequency 388.8 MHz  2 flip-flops per slice  8 phase-shifted clocks + 8 inverted clocks  TDC bin width: 160 ps  clock frequency 388.8 MHz  2 flip-flops per slice  8 phase-shifted clocks + 8 inverted clocks  TDC bin width: 160 ps

17. 128 channels with 16 TDC bins June 13, 2011Sebastian Schopferer17 Differential Nonlinearity

18. TDC time resolution June 13, 2011Sebastian Schopferer18  RMS of the time stamp difference between ‘channel n’ and the mean of all other channels: TDC time resolution < 0.5 * LSB = 80 ps TDC time resolution < 0.5 * LSB = 80 ps for comparison: resolution of ideal TDC = 1 / sqrt(12) * LSB = 46 ps

19. Conclusion June 13, 2011Sebastian Schopferer19 design objectives achieved:  128 TDC channels in the GANDALF Virtex-5 FPGA  TDC bin width: 160 ps  DNL < 0.2 LSB = 32 ps  time resolution < 80 ps rms under progress:  integrate 128 scaler channels into the same design  inter-board communication via VXS for fast trigger decisions  design migration to Artix-7 or Kintex-7 (front-end solution) more about the GANDALF module: http://hadron.physik.uni-freiburg.de/gandalf/