1. State Machines

3. Figure 13-17: General Model for Mealy Circuit Using Clocked D Flip-Flops

4. Figure 13-18: Minimum Clock Period for a Sequential Circuit

5. Figure 13-19: General Model for Moore Circuit Using Clocked D Flip-Flops

6. Figure 13-5: Moore Sequential Circuit to be Analyzed

7. Figure 13-6: Timing Chart for Figure 13-5
Analysis of previous circuit for input sequence X = 01101 1 1 1
Figure 13-6: Timing Chart for Figure 13-5

8. Figure 13-7: Mealy Sequential Circuit to be Analyzed
Mealy analysis for input sequence X = 10101
Figure 13-7: Mealy Sequential Circuit to be Analyzed

9. Figure 13-8: Timing Chart for Circuit of Figure 13-7

10. Figure 12-17: State Graph and Table for Up-Down Counter

11. Figure 12-18: Binary Up-Down Counter

12. Moore

13. Mealy