1. 1 Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains LIRMM CNRS / University of Montpellier II FRANCE J. DALMASSO, M.L. FLOTTES, B. ROUZEYRE

2. 2 Outline Introduction and motivation Serialization vs compression ? Compression technique Results Conclusion

3. 3 Needs for Test Data Compression  Integration density  Number of transistors  Number of faults to test  Test data volume  Test time  => Multiple scan chains  ATE limits: Memory depth # ATE channels

4. 4 Issue N scan chains, M ATE channels, N > M How to fit M with N ? CUT ATE N M

5. 5 1) Serialization of test data 1 Test slice 1 Pattern  Short test sequences (No X's) 1 test pattern = L test slices 1 test slice = divided into  N/M  slices of M bits in ATE

6. 6 2) Horizontal (de)compression

7. 7 Test pattern compression  Long test sequences (due to X's, low fill rate)

8. 8 Issues Given: M ATE channels, N scan chains, N > M  Fitting M with N ? –Serialization : short test sequences (No X's) –Compression: long test sequences (X's)  What is the best solution ?

9. 9 Proposed horizontal compression method  Features  Circuit netlist independent (suitable for IPs)  Test data independent (additional test patterns)  Specific tools independent  Low cost hardware decompressor  Input: test data sequence  actually applied to CUT  No impact on fault coverage  Take advantage of X's in test sequence

10. 10 Decompressor architecture N 000 0 Add Cells Output Shift Register To scan chains From ATE M

11. 11 a N-1 …………………………………..…...…….a 0 Decompression principle Let S i = a N-1 ………………..…...…….a 0 Let S i+1 = b N-1 …………………..………b 0 1/ it exists Sc i = c M-1 ……c 0 / S i+1 = S i + Sc i 000 0 c0c0 c1c1

12. 12 c0c0 c1c1 b N-1 …………………………………………..…b 0 Decompression principle Let S i = a N-1 ………………..…...…….a 0 Let S i+1 = b N-1 …………………..………b 0 1/ it exists Sc i = c M-1 ……c 0 / S i+1 = S i + Sc i 1 slice on N bits (S i+1 ) => 1 slice of M bits (Sci) in ATE 000 0 Remark : P(  c j : a i  b i ) = 1/ 2 dist => uniform distribution of inputs over adders dist

13. 13 Decompression principle Let S i = a N-1 ………………..…...…….a 0 Let S i+1 = b N-1 …………………..………b 0 2/ it does not exist Sc i = c M-1 ……c 0 => serial loading of S i+1 b 2M b M b 0 b 2M+1 b M+1 b 1 A slice on N bits (S i+1 ) =>  N/M  slices of M bits in ATE

14. 14 Compression Case 1 : it exists Sc i on M bits => 1 slice of M bits Case 2 : it does not exist Sc i =>  N/M  slices of M bits Compression –Maximize case 1 occurrences –Presence of X's Columns ordering X's assignment Pattern ordering

15. 15 S1:0X1X S2:11XX S3:X1X0 S4:1XXX S1:1XX0 S2:X1X1 S3:X10X S4:XXX1 Scan Chains ATE Channels Compression algorithm: columns ordering P(  c j : a i  b i ) = 1/ 2 dist

16. 16 Compression algorithm: X's assignment I = 1 If S C i Initialization of S i S i+1 = S i + S C i i++ NO YES S C i coded on M bits shift mode add mode S i coded on N bits S C i assignment END while i< #Slices

17. 17 Initialization and assignment S C 1 : 0 1 0 S C 2 : 0 1 0 S C 3 : 1 1 0 S C 4 : - - - S1:1XX0X1XX0 S2:XX1XX0X0X S3:X0XXX1XXX S4:X1XX000XX S5:XX01X01XX S1:101001000 S2:101010000 S3:101011000 S4:110100000 S5:XX01X01XX Init => ATE Channels Scan chains

18. 18 Compression algorithm: X's assignment I = 1 If S C i Initialization of S i S i+1 = S i + S C i i++ NO YES S C i coded on M bits shift mode add mode S i coded on N bits S C i assignment END while i< #Slices

19. 19 Compressed Slice assignment 000100101S1 X0X0XX1XXS2 XXX1XXX0XS3 XX000XX1XS4 XX10X10XXS5 ? abc S1 S2 S4 S3 S4 S5 0 1 1 1 1 1 0 0 1 0 1 0 1 1 0 a b c S5

20. 20 Example S C 1 : 0 1 1 S C 2 : 0 1 1 S C 3 : 1 1 1 S C 4 : 0 0 1 S1:1XX0X1XX0 S2:XX1XX0X0X S3:X0XXX1XXX S4:X1XX000XX S5:XX01X01XX S1:101001000 S2:101010001 S3:101011010 S4:110100011 S5:110100100 Init =>

21. 21 Pattern ordering V0 V1 V2 V3 V4 V1 V2 V4 V2 V4 V2 Pattern order has an influence on the number of compressed slices  Comparison of Pattern Ordering Algorithm:  Greedy algorithm  Simulated Annealing

22. 22 Decompression synchronization 00 Scan enable Control CLK S11000 S21001 S31110 S40110 S1 -> S2 : 0 1 S2 -> S3 : 1 1 S3 -> S4 : - - XXXX XXXX XXXX 1 0 X1X0 1 1 XXXX XXXX XXXX 0 0 1000 1 1 1000 XXXX XXXX 0 1 1001 1 0 1001 0001 XXXX 1 1 1110 1 0 1110 1001 1000 0 1 1001 1 1 1110 1001 1000 1 0 0110 1 1 0110 0111 1001 0 1 0111 1 0 Original test Sequence Compressed test Sequence FSM Sc 1 1 0 Sc 2 0 0 Sc 3 0 1 Sc 4 1 1 Sc 5 0 1 Sc 6 1 0

23. 23 Compression vs serialization Test Time (loading) = Depth Data Volume With Compression Serialization 1slice

24. 24 Experiments: Compression vs Serialization Test data sequences –Compression : X's needed type 1 : no compaction –long test sequences (very low fill rate) type 2 : compaction during ATPG –medium size test sequences –Serialization : No X's, type 3 : all ATPG optimizations enabled (fault dropping, random filling, compaction …) –short test sequences (fully specified) –ATPG

25. 25 Experimental results S5378 circuit (214 flip-flops)

26. 26 Experimental results N= 32 scan chains, M = 8 ATE channels

27. 27 Comparison with Circular Scan [*] [*] B. Arslan, A. Orailoglu, "CircularScan: a scan architecture for test cost reduction", DATE'04, pp: 1290-1295.

28. 28 Post process for regular circuits (not for IPs): Fault simulation => Pattern Dropping  Pattern rejection algorithm Compression & X’s Assignment Test Sequence with X’s Fully specified Test Sequence : T 1XX10X01 XX1XX10X P1: P2: f1, f2 f3 11010001 10110101 P1: P2: f1, f2 f3, f1, f2 T T* P Pattern P* Pattern With P* ≤ P

29. 29 Pattern Dropping Algorithm

30. 30 Conclusion Simple horizontal compression technique  Circuit netlist independent (suitable for IPs)  Test data independent  Specific tool independent Effective alternative to serialization  Compacted test sequences vs fully specified sequences

31. 31 Pattern Dropping Algorithm For i=1 to #P i in T If fd i > fd i-1 Add P i to T* Fault simulation of T* Number of detected faults: fd i i++ End For NO YES Remove P i from T* New test sequence T*

32. 32 Column Ordering Pattern Ordering Compression Pattern Dropping standard circuits only Compression process summary

33. 33 Perspectives  Other sequential decompressor structures  Co-optimization test architecture / compression test time: tam sizing / wrapper sizing / decompressor

34. 34 State Of The Art  At the CUT inputs (when test vectors are applied)  At the CUT outputs (when the test responses are checked)

35. 35 State of The Art Output Compression Time compaction (MISR based solutions) Risk of aliasing Diagnosis difficult »Koenemann (IBM) ITC’01 Spatial compaction (Xor trees based solutions) Presence of unknown values »Mitra ITC’02 Mixed methods e.g. Convolutional compactors »Rajski (MENTOR) ITC’04