1. ssh allows us to login to the system and “-X” enables X Windows support “pwd” – print working directory – should be your user directory “cd” – change directory into reference_design. “ls –alrt” – list directory contents. Other useful Linux commands: man top mkdir passwd cd ~ cd.. rm grep more cat Type xclock and you should see a clock appear if X Windows is working properly - shown on your screen but running remotely. Log in with Linux

2. cp –r ~grupo1/reference_design/ ~/. This will create a directory structure. RTL is where you should store your source verilog code. SYN is where you will perform synthesis. Update the script “dc_good.tcl” in scripts and invoke “dc_shell –f dc_good.tcl | tee logs/output.dc” PNR is where you will perform place and route. Update the script “icc_good.tcl” in scripts and invoke “ic_shell –f icc_good.tcl | tee logs/output.ic” CUSTOM is where you store reference files. Eg: matlab files that create test vectors and expected results, simulation will use these vectors and match the results. SIM is where you store your simulation files. Optional in this case. GOLDEN is where you store your final files – RTL, GDS, SDC, TB.v, and scripts. Copy the Reference Design

3. Simple reference design Two counters – one clocked by external clock, the other by an internally generated clock. All clocks have to be identified for static timing to work correctly. Total of 40 flip-flops no where near the limit in terms of area for this chip size. Only four outputs and two inputs, power and ground. Total is 8 pins. Design Compiler - Reference Design

4. cd to syn directory for synthesis Update the script “dc_good.tcl” for your design identify file and module name identify clocks and frequency Run “dc_shell –f ” to invoke script. Look in reports for quality of output This can be done in gui format as well – “dc_shell –gui” Design Compiler - Prepare for synthesis

5. Design Compiler - Checking synthesis During synthesis you should see output identifying all flip-flops. Make sure this make sense. I have two 20 bit counters in the reference design so this looks good. Also look for latches which indicates a problem in your RTL. All if statements need an else and if missing can cause latches.

6. After script is run, look for returns of 1 for all lines. 0 is a failure for the previous command. In results you will have a *postsynth.v as your netlist and a sdc file with timing info. Check the netlist to make sure it looks reasonable. In logs, you will see the commands and output. Search for errors and “0’s”. In reports, check all files thoroughly. Timing – check that critical path passes and is legitimate. Area – not too big. I will report numbers that are reasonable in class. Power is interesting but not very accurate. Power is data dependent but you can improve by adding switching data from the simulator VCS. Design Compiler - After synthesis

7. Design Compiler - Checking synthesis Top of the netlist should have your module name, IO’s and nets. You will see some starting with a back slash which is an escape character as some tools cannot handle square brackets and this is used to escape.

8. Design Compiler - Checking synthesis Tri’s will be inserted due to the IO’s being bidirectional. Also, look at the gates. DCX1 is a flip-flop. Scroll down to check all of the gates.

9. Design Compiler - Checking synthesis Pad_bidirhe are the IO cells and you should see other gates like NAND2X1. NAND2X1 is the smallest 2 input NAND gate. X1 means small and the 2 is the number of inputs. A and B are in and Y is the output pins normally.

10. Design Compiler - Timing report Worse case path for main clock. Through the adder from bit 0 to bit 19 as expected. 20 nS to complete and finished in 8.34 nS so time to spare – which means positive slack of 11.27 nS. Passed and made sense.

11. Design Compiler - Timing report Worse case path for internally clocked counter. Through the adder from bit 0 to bit 19 as expected. 20480 nS to complete and finished in 8.34 nS so time to spare – which means positive slack with over 20,000 nS of positive slack. Passed and made sense. Note that these timings are only for setup calculations and no holds are completed. Since the clock tree is not in place (ideal clock tree assumed) there is no clock skew which is required for hold violations.

12. Check for latches (should not exist) and that the basic numbers are expected. For the MOSIS chip, I expect that 3-5 times this area is possible. Design Compiler - Area report

13. IC Compiler - Place, route, timing and checks The icc_good.tcl script will go into the synthesis directory to obtain the netlist and sdc file (timing).

14. IC Compiler – First return – Floor Plan At first return – start_gui to invoke viewer. You will need to run to this point twice: once just to create an IO file and once to use the file renamed to is_pad.tcl with the source uncommented. cp set_pad_attributes_on_cell_xtal_chip_with_io.tcl is_pad.tcl Check that the file has all IO declared. Uncomment the “source is_pad.tcl” line in the script and run again.

15. IC Compiler – First return – Floor Plan

16. Use the ruler to check sizes of the die. 1500 microns is the max size for each side.

17. IC Compiler – First return – Floor Plan Change the visibility selections to see different layers. Pins and Site rows to see metals and where the standard cells will be placed later. Note that all unplaced cells are to the right – out of bounds for now.

18. IC Compiler Second return – Power and IO Fill

19. Should see power lines at all three levels and ring with vertical straps. IO Ring is complete but you must set the visual settings to “Max Quality”. Change levels to 1 or 2 to see into lower hierarchical levels. May need to change color of poly to see transistors.

20. IC Compiler Third Return – Placement of Cells

21. IC Compiler – Fourth Return - Clock Tree Invoke “Report Clock Tree”

22. IC Compiler – Fourth Return - Clock Tree

23. Selecting main_clock

24. IC Compiler – Fourth Return - Clock Tree Selecting “secondary_clock” – Note no IO included in this internal clock.

25. ======================= Clock Tree Summary ======================== Clock Sinks CTBuffers ClkCells Skew LongestPath TotalDRC BufferArea ----------------------------------------------------------------------------------------------- main_clock 39 12 14 0.0493 2.0112 0 4536.0000 second_clock 20 4 4 0.0311 0.9414 0 2016.0000 Post Routing (skew increased :/ ): ======================= Clock Tree Summary ======================== Clock Sinks CTBuffers ClkCells Skew LongestPath TotalDRC BufferArea ----------------------------------------------------------------------------------------------- main_clock 39 12 14 0.1113 1.9813 0 4536.0000 second_clock 20 4 4 0.0319 0.9401 0 2016.0000 1 IC Compiler – Fourth Return - Clock Tree In 90nm technology, 0.2 ns of skew was considered acceptable. Skew isn’t a problem if you pass hold timings though.

26. IC Compiler – Fourth Return - Clock Tree Check timing report in log. Need “Met” next to slack.

27. IC Compiler – Fourth Return - Clock Tree Check QoR report for hold violations after the tree.

28. IC Compiler – Fifth Return - Routing

29. IC Compiler – Well filler

30. IC Compiler – Metal Density Fill

31. verify_pg_nets Checking [gnd!]: There are no floating shapes All the pins are connected. No errors are found. Checking [vdd!]: There are no floating shapes All the pins are connected. No errors are found. Checked 2 nets, 0 have Errors Update error cell... 1 verify_lvs ** Total Floating ports are 14. ** Total Floating Nets are 0. ** Total OPEN Nets are 0. ** Total Electrical Equivalent Error are 0. ** Total Must Joint Error are 0. Check floating nets are on unused outputs of cells. This is ok. Check the reports directory for timing and QoR reports for passing all timing checks including holds. IC Compiler – Final Check Off

33. Check floating nets are on unused outputs of cells. This is ok. IC Compiler – Final Check Off

34. Data_in and Data_inB from IO must float if they are output pins. IC Compiler – Final Check Off

35. Custom Designer – Import GDS Go to “custom” directory and invoke “cdesigner”, create a library, read in the GDS, add metal 3 art (optional) and run final DRCs. We will be performing DRCs on the logic level and not check the IO’s as these are known to be good and have problems with DRC rules (on the to- do list to fix but just a minor annoyance now). Before you run the DRCs - you can use “add net” after selecting “metal3” and add metal art work. This can be saved as a cell in the library.

36. Custom Designer – Create new library Create “new library” to import stream the GDS into with the correct technology.

37. Custom Designer – Import GDS Import “stream” allows us to read in the GDS file created by IC Compiler and later to be sent to MOSIS for fabrication. The GDS shows all geometries of the fabricated device.

38. Custom Designer – File -> Import Stream IC Compiler script command: “save_mw_cel -as ${design_name}” determines the Top Cell. IC Compiler script command: “write_stream -lib_name MW_${design_name}_LIB -format gds results/${design_name}.gds determines the file name of the GDS filename.

39. Custom Designer – Open Layout

40. Custom Designer – Draw Images in Metal 3 Shift F – shows all lower hierarchical layers. F – fits the design to the window.

41. Custom Designer – Draw Images in Metal 3 Shift F – shows all lower hierarchical layers. This shows after shift F.

42. Custom Designer – Draw Images in Metal 3 On the right you can select metal 3 and the glasses icon to only see Metal 3. Control R – redraws after a change.

43. Custom Designer – Draw Images in Metal 3 On the right you can select create interconnect and draw lines. There is a submenu that allows you to change thickness and permitted angles.

44. Custom Designer – Run DRCs Before we can run checks, we must flatten the design. Open Hierarchical Navigator.

45. Custom Designer – Run DRCs Select flatten from edit menu.

46. Custom Designer – Run DRCs There will be “flatten” submenu in the tool bar and set the switches according to the picture below. With the mouse, select the entire design by dragging a box around everything. Then click the check mark on the far right of the menu. You should see only one instance with sub- instances in the Hierarchical Navigator after you click on the refresh.

47. Custom Designer – Run DRCs Use the verification menu to run final DRCs regardless of whether you added any metal patterns. Only select the core and avoid the IO’s as there is an issue with the rules for the cells which isn’t real.

48. Custom Designer – Run DRCs Use the verification menu to run final DRCs regardless of whether you added any metal patterns. Only select the core and avoid the IO’s as there is an issue with the rules for the cells which isn’t real.

49. Custom Designer – Run DRC Fill in the following fields of the DRC setup pane – “Main”. The runset file should be in your custom directory. Press the refresh button next to runsets.

50. Custom Designer – Run DRC If you press the refresh button in the Main panel next to the runsets, you should see fields in this “control variable” section. There are none in this picture as Hercules (DRC checker) was not yet installed.

51. Custom Designer – Run DRC In Custom Options, click the “select window” button and you will be allowed to select from the main window what will be DRC checked. Since there are problems in the IO that are not real DRCs and the IO’s are proven, we are only going to check the interior section of the chip. Select the interior by drawing a box around the chip but avoiding the IO rings. Coordinates will show in the field and should be similar to what is shown here – approximately 250, 1250, 1250, 1250. Now click OK to run DRCs.

52. Custom Designer – Run DRCs Run density_check.bash script on gds file.

53. MOSIS Submission Tutorial for ON Semiconductor 0.5u C5F CMOS

54. Example design and project details

55. Overview After being assigned a design name, number and password go to: www.mosis.com Select “fabricate request” and fill in the form for the secure https upload option Put your five digit number and password here.

56. Use your design number Run the crc program on your gds for these two numbers

57. Use your email address, phone number and design.

58. Put any information that will make receiving the chips easier