1. 1 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/24/2011 (Course Overview) Instructor: Dr. Phillip Jones (phjones@iastate.edu) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA http://class.ece.iastate.edu/cpre583/

2. 2 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Class Introduction Class Survey (by next class, phjones@iastate.edu) –Background (year in school, C programming, VHDL/Verilog, EE/CPRE background, ISU login ID) –What would you like to get from this class Syllabus Course Expectations –Reinforce research fundamentals –Asking the right question VHDL handbook (source Synplicity) –http://www.cs.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf (quick ref)http://www.cs.umbc.edu/portal/help/VHDL/VHDL-Handbook.pdf VHDL online tutorials –http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html –http://www.vhdl-online.de/tutorial/http://www.vhdl-online.de/tutorial/

3. 3 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Basic objectives and topics covered in this class. VDHL is NOT a programming language. It is a means to describe hardware. What you should learn

4. 4 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) Basic components of an FPGA ( Chapter 1 ) Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2) Examples of reconfigurable systems (Chapter3) Managing the reconfiguration of systems? (Chapter 4)

5. 5 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics A B X opcode {+, -, AND, OR} Behavior VHDL: ALU compnt ALU (A,B,opcode,X) case opcode when => opPlus X <= A + B; when => opSub X <= A – B; when => opAND X <= A and B; when => opOR X <= A or B; end case; end component; ALU Structural VHDL: ALU component ALU (A,B, opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X); end component; Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week)

6. 6 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) A B X opcode {+, -, AND, OR} A B X addAB subAB andAB orAB 4:1 Mux opcode {+, -, AND, OR} 2 Xadd Xsub Xand Xor ALU Structural VHDL: ALU component ALU (A,B, opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X); end component;

7. 7 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) Abstraction that allows –Reasoning about computation Correctness Extraction of parallelism –Transformations for optimization –Guarantee Properties FPGA Memory CPU

8. 8 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) Abstraction that allows –Reasoning about computation Correctness Extraction of parallelism –Transformations for optimization –Guarantee Properties Memory Function 1 Function 2 Function 4 Function 3

9. 9 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) Abstraction that allows –Reasoning about computation Correctness Extraction of parallelism –Transformations for optimization –Guarantee Properties Memory Function 5 Function 1 Memory Function 2 Function 3 Function 4 Memory

10. 10 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) Streaming Applications Data Parallel Applications Fix/Floating Point Computations Evolvable Hardware Performance Trade-offs

11. 11 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics A B addAB X A B xorAB X A B andAB X A B orAB X 0 0 1 1 0 1 A B X 01100110 0 0 1 1 0 1 A B X 01100110 0 0 1 1 0 1 A B X 00010001 0 0 1 1 0 1 A B X 01110111 2-input Look Up Tables (LUTs) FPGA LUT Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) X <= A+B;X <= A xor B;X <= A and B;X <= A or B;

12. 12 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics FPGA LUT addAB LUT xorAB LUT andAB LUT orAB LUT Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (2 Weeks) 4. Case Studies (1 Week) A B addAB X A B xorAB X A B andAB X A B orAB X 0 0 1 1 0 1 A B X 01100110 0 0 1 1 0 1 A B X 01100110 0 0 1 1 0 1 A B X 00010001 0 0 1 1 0 1 A B X 01110111 2-input Look Up Tables (LUTs) X <= A+B;X <= A xor B;X <= A and B;X <= A or B;

13. 13 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Main topics Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about. Please give suggestions as the semester progresses. Agenda 1. Overview (6 Weeks) a. Reconfigurable HW b. VHDL 2. Computation Models & Architectures (4 Weeks) 3. Mapping logic to FPGAs (3 Weeks) 4. Case Studies (1 Week)

14. 14 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks)

15. 15 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) ML507 Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks)

16. 16 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks)

17. 17 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Serial UART Echo.vhd

18. 18 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Serial UART Echo.vhd (Modify to capitalize only (a-z))

19. 19 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Echo.vhd Ethernet (UDP/IP)

20. 20 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Echo.vhd (Modify to count strings (e.g. corn!)) Ethernet (UDP/IP)

21. 21 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

22. 22 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

23. 23 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) FPGA PC Display.c Ethernet (UDP/IP) Power PC User Defined Instruction Monitor VGA

24. 24 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problems (MPs) Agenda 1. Platform Introduction 2. Network String Matching 3. Image: PPC coprocessor 4. Final Projects(~6 weeks) Choose your own topic Groups of 3-4 (maybe 5 for case by case) Encouraged to take on aggressive projects

25. 25 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Review Syllabus Objects Expectations Grading breakdown MP grading policy: (more flexible for Distance Students) –Up to 5% added for early completion (Fri Midnight) –-5% after Fri Midnight –-10% additional after Monday Midnight –-10% additional after Tue Midnight –After Wed Midnight will make a note.

26. 26 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What is Reconfigurable Computing? Ask wiki: http://en.wikipedia.org/wiki/Reconfigurable_computing http://en.wikipedia.org/wiki/Reconfigurable_computing Computing on a medium that is not fixed Examples: –rDPA (course grain reconfiguration) –FPGA (fine grain reconfiguration) –General Purpose Processor (not really) underlining hardware typical executes a relatively small fixed instruction set.

27. 27 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are rDPAs? rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

28. 28 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are rDPAs? rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

29. 29 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are rDPAs? rDPA: reconfigurable Data Path Array Function Units with programmable interconnects ALU Example

30. 30 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are FPGAs? FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

31. 31 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are FPGAs? FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

32. 32 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) What are FPGAs? FPGA: Field Programmable Gate Array Sea of general purpose logic gates CLB Configurable Logic Block

33. 33 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB

34. 34 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z 4 input Look Up Table 0000 0001 1110 1111 ABCD Z

35. 35 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z 4 input Look Up Table 0000 0001 1110 1111 ABCD Z 00010001 AND Z A B C D

36. 36 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z 4 input Look Up Table 0000 0001 1110 1111 ABCD Z 01110111 OR Z A B C D

37. 37 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z 4 input Look Up Table X000 X001 X110 X111 ABCD Z 01110111 2:1 Mux C D B Z

38. 38 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z

39. 39 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z DFF PIP Programmable Interconnection Point

40. 40 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some FPGA Details CLB LUT A B C D Z DFF PIP Programmable Interconnection Point

41. 41 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) FPGA Usage Models Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC) Experimental ISA Experimental Micro Architectures Image Processing Computational Biology CPU + Specialized HW - Sparc-V8 Leon Remote Update Fault Tolerance Run-time adaptation Run-time Customization

42. 42 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Application Area for Acceleration

43. 43 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Development Platform Overview ML507 Evaluation Platform User Guide (pgs. 14-16) –http://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdfhttp://www.xilinx.com/support/documentation/boards_and_kits/ug347.pdf

44. 44 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Machine Problem 1 (MP1) Short Overview Assigned Fri (8/27), Due Friday (9/10). Purpose: Make sure you can run the tools. Very light VHDL coding. Primary Tasks: –Run the echo circuit without modifications –Run the echo circuit with a modification to convert lower case ASCII characters to upper case. Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from: –For Windows: http://www.nomachine.com/download-client-windows.phphttp://www.nomachine.com/download-client-windows.php –For Linux: http://www.nomachine.com/download-client-linux.phphttp://www.nomachine.com/download-client-linux.php –For MAC OS: http://www.nomachine.com/download-client-macosx.phphttp://www.nomachine.com/download-client-macosx.php –For Solaris: http://www.nomachine.com/download-client-solaris.phphttp://www.nomachine.com/download-client-solaris.php

45. 45 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) VHDL basics VHDL: (V)HSIC (H)ardware (D)escription (L)anguage –VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit It is NOT a programming language!!! It is a Hardware Description Language (HDL) Conceptually VERY different form C,C++ Some links to VHDL tutorials –http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.htmlhttp://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html –http://www.vhdl-online.de/tutorial/http://www.vhdl-online.de/tutorial/ –http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf

46. 46 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C is inherently sequential (serial), one statement executed at a time VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time

47. 47 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

48. 48 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

49. 49 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 1 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

50. 50 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1

51. 51 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step”

52. 52 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 1 B = 1 C = 1 X = 1 Y = 1 Z = 1 Ans = 1 “Simulates in parallel ever delta time step” Snap shot after input change

53. 53 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

54. 54 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Different

55. 55 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step” Snap shot after input change

56. 56 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 2 “Simulates in parallel ever delta time step”

57. 57 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Some Key Differences from C C example VHDL example A = B + C X = Y + Z Ans = A + X Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 Current Values: A = 2 B = 1 C = 1 X = 2 Y = 1 Z = 1 Ans = 4 “Simulates in parallel ever delta time step”

58. 58 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step”

59. 59 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1)

60. 60 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2)

61. 61 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Corresponding circuit VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C X <= Y + Z Ans <= A + X “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4)

62. 62 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Corresponding circuit (More realistic) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(1) X(1) Ans(1) 2ns

63. 63 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(2) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

64. 64 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) VHDL example Initially: A,B,C,X,Y,Z,Ans =1 “Simulates in parallel ever delta time step” + + B(1) C(1) Y(1) Z(1) + A(2) X(2) Ans(4) Corresponding circuit (More realistic) 2ns A <= B + C after 2ns X <= Y + Z after 2ns Ans <= A + X after 2ns

65. 65 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Typical Structure of a VHDL File LIBRARY ieee; ENTITY test_circuit IS PORT(B,C,Y,Z,Ans); END test_circuit; ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0); BEGIN A <= B or C; END Include Libraries Define component name and Input/output ports Declare internal signals, components Implement components functionality

66. 66 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Next Lecture Basic components of an FPGA VHDL overview cont.

67. 67 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Questions/Comments/Concerns

68. 68 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Fast Prototyping Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC)

69. 69 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Highly Parallel Applications Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC)

70. 70 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) System on Chip (SoC) Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC)

71. 71 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Full Reconfiguration Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC)

72. 72 - ECpE 583 (Reconfigurable Computing): Course overview Iowa State University (Ames) Partial Reconfiguration Fast Prototyping Partial Reconfiguration Full Reconfiguration Parallel Applications System on Chip (SoC)