1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 2 Eike Schweißguth, Arne Wall Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Agenda Multiplier Adder Pipelining Metric Frequency Response

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Multiplier – Modification of the Coefficients reduced size of coefficients from 16 bits to 10 bits (deleted lower 6 bits)  less area on chip; more speed due to shorter adders Booth encoded coefficients lead to a maximum of 3 partial products use of hard wired multipliers Shortened CoefficientBooth Encoded Coefficient 1 1 1 1 1 1 0 1 1 1-1 1 0 0 -1 1 1 1 1 1 1 0 0 0 0-1 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 -1 0 0 1 1 1 1 1 0 0 0 0 0 0-1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0-1 0 1 0 -1 0 0 0 ……

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Multiplier – Structure of the Multiplier Adder Register Adder Register Partial Products Previous Coefficient Register

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Adder optimized carry path on Virtex 6 FPGA  fast Ripple Carry Adder use of Ripple Carry Adder instead of Carry Increment Adder consideration to use Carry Increment Adder on the ASIC easy exchange of adders possible in VHDL-Code

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Pipelining implemented Direct Form II of the FIR-filter 2 additional pipeline stages between the adders of the multiplier maximum of one adder in one pipeline stage too many register stages require more area and let the metric decrease 3 pipeline stages used in the design

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Pipelining the expected increase in frequency can be confirmed Max # of Adders in one PipelinestageMaximum Frequency [MHz] 3Approx. 100 2Approx. 160 1Approx. 300

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 8 Metric after Synthesis Frequency f [MHz]309.023 Area A [# of LUT-FF-Pairs]2605 # of Pipeline Stages3 Metric [MHz^3]12.973 # Slice LUTs2420 # Slice Registers940

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 9 Metric after Place & Route Frequency f [MHz]310.559 Area A [# of LUT-FF-Pairs]2147 # of Pipeline Stages3 Metric [MHz^3]15.461 # Slice LUTs2061 # Slice Registers940

10. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 10 Metric of first Design Frequency f [MHz]39.619 Area A [# of LUT-FF-Pairs]38 # of Pipeline Stages1 Metric [MHz^3]0.016 # Slice LUTs8836 # Slice Registers439

11. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 11 Frequency Response Low Influence of modified Coefficients

12. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 12 Thank you for your attention!