1. EE210 Digital Electronics Class Lecture 2 March 27, 2008

2. Introduction to Electronics
4/22/2017
Introduction to Electronics 2

3. 1.4.6 Amp Power Supplies
Power supplied to Load by Amp is Greater than Power Drawn from Input Signal
To supply that extra power the Amp Need DC Power Supplies for their Operation
In addition the DC PS supply power that might be Dissipated in Internal Amp Ckt

5. Power Deliverd to Amp Pdc = V1I1 + V2I2
Amp Power-balance Eq. Pdc+ PI = PL + Pdissipated

6. Amp Efficiency η ≡ (PL / Pdc) x 100
What about PI and Pdissipated ??
Power Efficiency is Important Performance Parameter for Amps that Handle Large Amounts of Power …
… and Such Power Amplifiers are Used as Output Amps of Stereo Systems

7. Simple Ckt Diagram – We shall adopt the convention illustrated and will not Explicitly show connections of Amp to DC PS

8. Example 1.1 (Page 17)
Data Given;
V1=V2= 10V
I1 = I2 = 9.5 mA
vI = 1 V, vO = 9V
RL = 1kΩ
iI = 0.1 mA
Find:
Av, Ai, Ap,Pdc, Pdissipated, η

9. 1.4.7 Amp Saturation
Practically Amp Transfer Characteristics Only Remain Linear for Limited Range of I/O Voltages
Amp Operated from 2 PS the Output Voltage can not exceed specified positive limit and can not decrease below specified negative limit

10. An Amplifier Transfer Characteristic
An Amplifier Transfer Characteristic. vI Must be kept within Linear Range of Operation.

11. 1.4.8 Nonlinear TC and Biasing
Except from output Saturation Effect the Amp TC have been assumed linear
In Practical Amps the TC may exhibit nonlinearities of various magnitudes
Biasing is a Simple Technique to Obtain Linear Amplification From Amp Having Nonlinear TC

12. Considerable Nonlinear Amp TC.
Amp is Biased to Obtain Linear Operation and the Signal Amplitude is Kept Small

13. Time-varying Signal to be Amplified is Superimposed on the DC Bias VI and Total Instantaneous Input vI(t) = VI + vi(t)
And vO(t) = VO + vo(t)
With vo(t) = Av vi(t)
Where Av = dvO / dvI |at Q is the Slope of Almost Linear Segment of TC
This Way Linear Amplification is Achieved with a Limitation of Keeping Input Signal Sufficiently Small

14. Example 1.2
(Page 21)
Example 1.2 Transfer Characteristic of Amplifier. Note That Amplifier is Inverting (Negative Gain)

15. 1.4.9 Symbol Convention Terminology and Symbol Convention to be Used
Instantaneous Quantities Lower Case Symbol with Uppercase Sub iA(t), vC(t)
DC Quantities Upper Case Symbol Uppercase Sub IA, VC
PS (dc) Voltages Uppercase V with Double-letter Uppercase Sub, VDD Similar notation for Current from PS
Incremental Signal Quantities Lowercase Symbol with Lowercase Sub ia(t), vc(t)
Sine Wave Signal Amplitude Uppercase Letter with Lowercase Sub Ia, Vc

16. Symbol Convention Employed

17. 1.7 Digital Logic Inverters
Logic Inverter is a Most Basic Element in Digital Ckt Design
Plays a Role Parallel to the Amp in analog Ckt
We will get Introduced to Logic Inverter in This Section

18. 1.7.1 Function of the Inverters
Logic Inverter INVERTS the Logic Value of its Input Signal
That is for 0 input, out put will be 1, and vice versa
In Voltage Level Terms
When vI is Low (close
to 0) the vO will be
high VDD

19. 1.7.2 The Voltage Transfer Characteristic
VTC to Quantify Operation of Inverter
Observe the TC of Amplifier in Ex 1.2
This Inverting Amp can
be used as Inverter
when we use its
Extreme Regions
of Operation –
Opposite to Amp
Dig App Make Use of
Gross nonlinearity exhibited by VTC

20. VTC of an inverter.
VOH Does Not Depend on Exact Value of vI as long as vI ≤ VIL.
When vI > VIL Inverter in Amp mode or Transition Region.
VIL is Max Value That vI Can Have While Being Interpreted by Inverter as Representing Logic 0.
VOL Does Not Depend on Exact Value of vI as long as vI ≥ VIH.
VIH is Min Value That vI Can Have While Being Interpreted by Inverter as Representing Logic 1.

21. 1.7.3 Noise Margins
Insensitivity of Inverter Output to Exact Value of vI within allowed regions is great advantage over analog ckts.
To Quantify Insensitivity Consider One Inverter Driving Similar Inverter
Noise Margin for High Input NMH = VOH – VIH
Noise Margin for Low Input NML = VIL - VOL

22. Four Parameters VOH,VIH,VIL, and VOL Define VTC of Inverter and Determine its Noise Margin, Which in Turn Measures its Ability to Tolerate Input Signal Variations
VOL: Output Low Level
VOH: Output High Level
VIL: Max Input as Logic 0
VIH: Min Input as Logic 1
NML: Noise Margin for Low Input = VIL - VOL
NMH: Noise Margin for High Input = VOH – VIH

23. 1.7.4 The Ideal VTC What Makes an Ideal VTC for Inverter?
Ideal VTC Maximizes the Noise margins and Distributes Them Equally B/W the Low and High Regions
VOH is at Max Possible Value VDD
VOL is at Min possible Value 0 V

24. The Ideal VTC (Cont…) VIL and VIH are equal at Mid of (VDD/2)
Width of Transition Region (Imp for Amp) is Zero
Steep Transition at Threshold Voltage (VDD/2) – Gain infinite
Noise Margins are Equal
NMH = NML = VDD/2
CMOS Inverter Has Close to Ideal VTC

25. 1.7.5 Inverter Implementation
Implemented using Transistors Operating as Voltage Controlled Switches

26. Transistor Switches are NOT Perfect
Their OFF Resistance is High, But
ON Resistance is not Zero and Some BJTs Exhibit Offset Voltage as well
The Result is That When vI is High VOL Is not Ideally Zero

27. More Elaborate Implementation Exists Utilizing Pair of Complementary Switches (CMOS Based). When I/P Low, VOH = VDD, No Current Flows When I/P High, Ron Connect Ground, VOL = 0

28. Implementation Using Double-Throw Switch (ECL Chap 7 & 11)
Steer IEE into one of two resistors Connected to +ve PS VCC
Connected to RC1 Logic Inversion-function at vO1
Output Voltage is Independent of Switch Resistance

29. 1.7.6 Power Dissipation
Digital Systems use large number of Logic Gates
Space and Economy Require as Few IC as Possible
Hence, As Many Logic gates As Possible on IC Chip
In Present VLSI 100K+ gates on IC
To Keep Acceptable limit of Power Dissipation in Chip, Power Dissipation/Gate Must be Minimum
Power Dissipation is Very Important Performance Measure of Logic Inverter

30. When vI Low no Power Dissipated
In other State Dissipation is V2DD/R and is Substantial
This Dissipation Occurs even When Inverter not Switching -- Static Power Dissipation

31. This Inverter Exhibit No Static Power Dissipation
BUT …

32. There is Always A component of Power Dissipation Due to Capacitance
Cap Exists between Output Node of Inverter and Ground
Internal Cap of Switches
Wires Connecting Output to Other Ckts have Cap
Input Cap of Any CKt Driven by Inverter

33. When Inverter is Switching from One State to Another, Current must Flow thru Switches to Charge and Discharge the Load Capacitance
The Current Give Rise to dissipation Called Dynamic Power Dissipation (Chap 4)

34. 1.7.7 Propagation Delay
Inverters are Characterized in Terms of The Time Delay Between Switching of vI (Low to High) and Corresponding Change Appearing at the Output
2 Reasons for Propagation Delay:
Transistors (Switches) Exhibit Finite (nonzero) Switching Time
The Cap needs to Charge/Discharge before Output Change
To Analyze Inverter Switching Need to Understand Time Response of Single-Time-Constant Ckts (STC) [Appendix D]

35. Step Function Applied to an STC Network with Time Constant τ, Out put at any time:
y(t) = Y∞ - ( Y∞ - Y0+)e-t/τ
Y∞ is final value where response is heading
Y0+ value of response immediately after t=0
Output at any time t is difference between final value and gap whose initial value is Y∞ - Y0+ and shrinking exponentially

36. Example 1.6 Before t=0 vI is high, and VOL is = Voffset + V in Ron
At t=0 SW opens, V across Cap cannot change instantaneously, therefore at t=0+ O/P is still Cap charges thru R and vO rises exponentially toward VDD

37. Using vO(∞) = 5 V and vO(0+) = 0.55V in Eq.
y(t) = Y∞ - ( Y∞ - Y0+ )e -t/τ
vO(t) = 5 – (5 – 0.55) e-t/τ
τ = RC. To find tPLH
vO(tPLH) = 0.5(5+0.55)
tPLH = 0.69τ
= 0.69RC
= 0.69x1000x10-11
= 6.9 ns

38. Formal Definitions of Propagation Delay of Inverter
Formal Definitions of Propagation Delay of Inverter. I/P with Finite Rise and Fall Time is applied, Inverted O/P Exhibits Finite Rise and Fall times. There is also delay time between I/P and O/P waveforms. Usually Prop. Delay is Specified by the average of hi-lo Prop. and lo-hi Prop. and measured at 50% of I/P and O/P waveforms.

39. HW #1 Problems at the end of Chapter 1: Prob. 1.30 Prob. 1.35
Due Next Week: 3 April 2008

40. In Next Class We Will Discuss: Chap 3 Diodes 3.1 The Ideal Diode
Topics:
3.1 The Ideal Diode
3.7 Physical Operation of Diodes
3.9 The SPICE Diode Model and
Simulation Examples