1. Green cavity progress Botao Jia botaoj@jlab.org May 17 2007 Advisors: Dr. Nanda Sirish, Dr. Wu Ying HAPPEX Collab. Mtg. May 17-18, 2007

2. 8GeV 4GeV 1GeV λ=1064nm 8GeV 4GeV 1GeV λ=532nm Motivation of upgrade Gain: 7000 15000

3. Optical Layout Faraday Isolator Vacuum Gauge

4. Cavity Locking Use Pound-Drever-Hall method to extract the phase of the resonace by using frequency modulation of the main laser beam. The phase of the resonace is used as the error signal in the feedback loop. 1. Using Mirror Piezo2. Using Laser Piezo PID- Regulator Non-tunable Laser Phase Modulator Beam Splitter Cavity Photo detector Oscillator Phase Shifter Mixer Low Pass Filter 0 Error signal Photo detector Beam Splitter Cavity Oscillator Phase Shifter Mixer Low Pass Filter 0 Tunable Laser PID- Regulator Error signal

5. FSR=170 MHz, Cavity bandwidth=80 kHz Snapshot of oscilloscope FSR=170 MHz, Cavity bandwidth80 kHz, The error signal

6. Fast and Slow ramps Slow ramp -> Finding the TEM00 mode, creating a single transmission peak Fast ramp -> At a certain TEM00 mode, creating multiple peaks Slow ramp Fast Ramp Transmission peaks

7. Previous locking by mirror piezo Feedback signal Error signal reflection transmission PZT Previous locking was not stable, poor resolution of the piezo drive caused oscillations.

8. 1064nm 532nm Innolight GmbH, Germany 809 nm Pump Diodes 1064 nm Nd:YAG 532 nm SHG via PPKTP Promethues green laser Index of Modulation Modulation frequency PZT resonace Choose operation fre 600-1000

9. Current locking by laser piezo Frequency feedback Error signal transmission reflection PZT locking has been achieved by feeding the error signal to the laser piezo.

10. Locking monitored via Epics Reflection Temperature Scan Transmission 6 mins min Locking for several mins duration has been achieved. 1. Regualtor is able to recover quickly within milliseconds. 2. Fluctuations are huge. Have to improve signal to noise ratio. 3. Goes out of lock. We are working on extending lock from mins to hour level.

11. Microcontroller based locking system ARM7 TDMI core, 16-bit/32-bit 44 MHz RISC Processor Multichannel, 12-bit ADC, 12 bit DAC Fast ramp Slow ramp PDT signal Fast ramp Slow ramp PDT signal So far we made good progress in being able to search for strong mode and generating lock trigger.

12. Conclusions: Minutes level locking has been achieved. The longest record so far is 6 minutes. Investigating stability issues to achieve hours level locking. Thank You