1. Part A Presentation High Speed Digital Signal Lab Students: Lotem Sharon Yuval Sela Instructor : Ina Rivkin

2. Cross Hole Ultrasonic Monitor (CHUM) system made by Piletest Quality control of deep concrete foundation Ultrasonic waves through the concrete Measuring the energy and the first arrival time Background

3. Motivation The current CHUM uses sample rate of 500kHz, complying American standard. A necessity came up to comply with the 1MHz French standard.

4. Goal Developing a board based on FPGA, that samples data at rates of up to 1MHz, and connects to the Motherboard. Enabling a high sampling rate and a slow data transfer rate to the MC by FPGA configured as a FIFO and as a data flow controller.

5. Data Flow Scheme ADC FPGA (FIFO) Micro- Controller Analog from Rx High speed Low speed To user interface Analog Devices AD7671 LQFP48 Analog to Digital Converter Altera FPGA Cyclone IV EP4CE6 EQFP144 Texas Instruments Micro-Controller MSP430F5419AIPZ, on the motherboard 1MHz

6. Motherboard - Power Supply Circuit - Microcontroller - Test Circuit - Variable-Gain Amplifier - Emitter Circuit System Overview Daughter Board

7. Project Overview Part I Electrical scheme PCB design PCB manufacturing & assembly Board power supply and FPGA examination Part II Board examination FPGA logic design: FIFO & state machine Microcontroller software Whole system operation examination Flash configuration device

8. Our Board ADC 16-Bit Data PROM 8-Bit Data Control Clock RESET Motherboard JTAG Control POWER Analog input Oscillator FPGA

9. Top ConnectorsFPGAADC JTAG Connector Motherboard connectors

10. Connectors

11. FPGA Power

12. FPGA I/O

13. FPGA Configuration (0,1,0) -> (1,0,0)

14. ADC

15. Oscillator

16. PCB Design 6 layers:

17. Structure of Our Board FPGA ADC Flash Config. Device JTAG & Motherboard Connectors Serial Resistors Operational Amplifier & Voltage Reference

18. Successful Tests Electrical verification: GND & supplies FPGA recognition via JTAG JTAG configuration Simple design trial run, using CLK from the MC (motherboard) and SignalTap

20. System Integration Ultrasound receiver Ultrasound emitter Motherboard ADC Daughterboard User Interface FIFO (FPGA) Control (FPGA) 16 8 Software (Microcontroller) Analog USB Analog Emitter circuit Receiver circuit

21. Controller (VHDL State Machine) FPGA Top Level Design Motherboard -> <- ADC

22. Idle FIFO Full= 0 wrclk = 1 FIFO Full= 1 Count=0 Rdclk = 1 St. Mach. Start= 0 Sample Rate= 0 Busy= 1 St. Mach. Start= 1 Busy= 0 wrfull= 1 FIFO RD= 0 FIFO RD= 1 FIFO RD= 0 FIFO RD= 1 FPGA State Machine FIFO RD= 1 FIFO RD= 0 H/L Byte =0 FIFO RD= 0 H/L Byte =1 FIFO RD= 0 Sample Rate= 1 wrfull= 0 STMACH_RST= 1 Rdclk = 1 Rdclk = 0

23. Interface to UI computer Data transfer from FPGA to the computer Receiver circuit gain control Emitter control Self test simulation control Microcontroller Software

24. Gantt