1. Presented by : Maya Oren & Chen Feigin Supervisor : Moshe Porian Lab: High Speed Digital System One Semester project – Spring 2014 1

2. Introduction Project Goals Requirements Top Architecture Micro Architecture Testing Problems & Solutions Conclusions 2

3. 3 A Picture In Picture is an additional video\picture data placed in a main video data frame. Commonly used in varies applications: Surveillance camera Television Computers

4. “Smart” Algorithm – Picture In Picture Implementing a synthesizable solution with VHDL Using testing environment 4

5. Internal communication via Wishbone protocol Input - External video (simulated as text) Output - Grayscale image resolution 800x600 pixels Main clock freq. 100MHz VESA (monitor) freq. 40 MHz 5

6. PIP Display WBS VGA Display WBM VESA TX Path Memory Management Memory Management RX Path SDRAM Controller WBS WBM WBS Host (Matlab) IS42S16400 SDRAM WBM UART Wishbone INTERCON 6

7. 7 Reg VESA CONTROLLER State Machine WBS Clk Rese t FIFO WBM 40 MHz 100 MHz dcFIFO FIFO Sync WBS Small Frame1 Small Frame2 Large Frame 800 x 600

8. 8 WBMFIFO REG WBS PIP DC FIFO VESA Sync

9. FIFO – Small 1 8 bit FIFO – Small 2FIFO – Background x800 Small Frame 1 Small Frame 2 Backgroun d Frame

10. 10 FIFO – Small 1FIFO – Background Dc-FIFO

11. 11 2 Counters (hcount, vcount) Default State – Large PIC Update from Reg – Start of Frame VSync – Changing Frames (x=800,y=600)

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13. startReg_insertPic_checkstayPics in lineEach pixelSynchronizeNew_line 13 Vsync = ‘1’ idle Valid_reg = ‘1’ Check the boundaries (y, len) and decide which pictures are in the current line Insert the registers values Choose which state according to pic_check States that indicates which pictures are in the current line Check the boundaries (x, width) and decide which pixel to transfer to dc-fifo Req_ln_trig = '1' and vcount<599 Vsync = '1' and vcount>=599 Vcount = vcount+1 Vcount = 0 Hcount = 0

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16. Dividing the components into testing groups by their functionality Testing the components as “stand alone” and groups of components by using TB Testing the “input group”, “output group” and the entire project, by using a testing environment. 16

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19. 19 PIP Block WBSWBS Read From TXT WBMWBM VESA VESA Collector WBSWBS Read From TXT WBMWBM WBSWBS WBMWBM WBS TB – Clk, Rst, Registers

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26. 26 An image generated by VESA when the NOT was a synchronous

27. Planning and Specifying a project Writing reusable, generic and synthesizable code Integration of many components Verify logic correctness using waveforms, text files. Documentation of the work done