1. Conversion from one number base to another Equation simplification Conversion to/from SOP/POS Minimization using Karnaugh Maps Minterm and Maxterm Equations Determining Prime Implicants and Essential Prime Implicants Logical completeness Using MUXs and ROMs to implement logic Timing Analysis The internal structure of flip-flops Flip-flop timings Rising and falling edge triggered flip-flops Counters and state machines Generating next state equations from counter sequences. Implementation using RS, D, T and JK flip-flops Determining next states from schematics Moore vs. Mealy State Graphs Completeness and conflict issues Creating transition tables and next state equations from state graphs Verilog code One-hot encoding LC3 control UART Review for Final Exam

2. Conversion from one number base to another

3. Equation simplification (X + Y)(X + Z) = (X + YZ) X + XY = X X + X’Y = X + Y X + XY = X

4. Conversion to/from SOP/POS (X + YZ) = (X + Y)(X + Z)

5. Minimization using Karnaugh Maps AB CD00011110 001 011111 11111 10111 AB + C’D + A’B’C + ABCD + AB’C AB + C’D + B’C

6. Minterm and Maxterm Equations F(ABCD) =  m (0,2,4,7,9,12,14,15) AB CD00011110 00111 011 1111 1011 BC’D’ + BCD + ABC + A’B’D’ + AB’C’D

7. Determining Prime Implicants and Essential Prime Implicants AB CD00011110 00111 01111x 11xx1 101 6 prime implicants 3 essential prime implicants

8. Logical completeness Inverter AND gate NAND AND gate Inverter OR gate

9. Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 for AB=00, Z=0 0

10. Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 for AB=01, Z=1 1

11. Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 for AB=11, Z=C’ C’

12. Implementing Logic Functions With Muxes Implement: Z = A’B + BC’ 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0

13. Implementing Logic Functions With Muxes An alternate method 4-to-1 MUX Z A B I0I1I2I3I0I1I2I3 0 1 C’ 0 Z = A’B + BC’ A=0 B=0 A=0 B=1 A=1 B=0 A=1 B=1 Z = 1 0 + 0 C’ = 0 Z = 1 1 + 1 C’ = 1 Z = 0 0 + 0 C’ = 0 Z = 0 1 + 1 C’ = C’

14. Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

15. Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

16. Using a ROM For Logic Specify a truth table for a ROM which implements: F = AB + A’BC’ G = A’B’C + C’ H = AB’C’ + ABC’ + A’B’C

17. Timing Analysis A B AB E C D CD F E+F X

18. Timing Analysis A B AB E C D CD F E+F X

19. Timing Analysis A B AB E C D CD F E+F X

20. Timing Analysis A B AB E C D CD F E+F X

21. Timing Analysis A B AB E C D CD F E+F X

22. Timing Analysis A B AB E C D CD F E+F X

23. Timing Analysis A B AB E C D CD F E+F X

24. The internal structure of flip-flops R S Q Q’ GATE GS GR D Q’ Q GATE D CLK Q Q’ D-type Flip-Flop

25. The internal structure of flip-flops T-type Flip-Flop CLK Q Q’ T

26. The internal structure of flip-flops JK-type Flip-Flop CLK Q Q’ J K

27. Flip-flop timings Clock-to-Q D CLK Q Q’ t CLK ! Q = t NOT + t AND + 2 x t NOR

28. D CLK Q Q’ t setup = t NOT + t AND + 2 x t NOR Flip-flop timings Setup time

29. D CLK Q Q’ t hold = t NOT Flip-flop timings Hold time

30. Flip Flop Timing CLK D Q t setup t hold t CLK ! Q time

31. D CLK Q Q’ Falling Edge Triggered DFF Rising and falling edge triggered flip-flops

32. Rising Edge Triggered DFF D CLK Q Q’ Rising and falling edge triggered flip-flops

33. Generating next state equations from counter sequences. Desired count sequence = 00 01 00 10 11 00 … If current state = 00, next state = ????? Implemented count sequence = 000 001 100 110 011 000 … N2 = Q2 Q1’ + Q1’ Q0 N1 = Q2 N0 = Q2’ Q0’ + Q1 Q0’

34. Implementation using RS, D, T and JK flip-flops

35. Determining next states from schematics Q0 Q2 CLK Q1 CLK Q2 D Q Q2 Q1’ Q0 Q2’ Q0’ Q1 Q0’ Q2 Q1 Q0 0 0 0 0 0 1 1 0 0 1 1 0 Initial state

36. Moore vs. Mealy

37. For general purpose FSMs, the encoding of the states is usually not significant For example, in the following state graph, the Encodings of the state are irrelevant … Event 1 Event 2 Event 1 Event 2Event 3

38. Completeness Issues In order for a state graph to be complete: It must completely specify the FSM Paths leaving a state must specify all POSSIBLE cases To check for completeness, OR together all of the exiting paths. If the result is “1” then the design is complete.

39. In order for a state graph to be conflict free: It must completely specify the FSM For a given set of input conditions, the transition from a state must be unique To check for conflicts, AND together all pairs of the exiting paths. If the result is “0” for all pairs, the design has no conflicting transitions. Conflict Issues

40. Creating transition tables and next state equations from state graphs

42. The resulting next state and output equations are: N1 = Q0 + Q1 TDONE’ N0 = TOKEN Q1’ Q0’ CLRT = Q0 SPRAY = Q1

43. Dataflow Operators

44. IR ALU PC AB

45. LC-3 Instructions ADD 0001 DR SR1 00 SR2 0 ADD 0001DRSR1 imm5 1 AND 0101 DR SR1 00 SR2 0 AND 0101DRSR1 imm5 1 BR 0000n z p PCoffset9 JSR 01001 JMP 1100000000000 BaseR LD 0010PCoffset9 DR LDI 1010PCoffset9 DR LDR 0110offset6 DR BaseR LEA 1110PCoffset9 DR NOT 1001 DR SR 111111 RET 1101 RTI 1000000000000000 STR 0111offset6 SR BaseR TRAP 1111trapvect80000 ST STI 0011 PCoffset9 SR 1011 PCoffset9SR PCoffset11 1100000000000 111 reserved JSRR 0100000000000 BaseR