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1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.

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Presentation on theme: "1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University."— Presentation transcript:

1 1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University

2 2 Outline Background and previous works Problem formulation Improved probabilistic coupling capacitance model Antenna avoidance through tree partitioning Layer assignment heuristic Experimental results

3 3 Coupling capacitance Coupling capacitance (crosstalk) induces two different problems: Functional noise: Delay noise: Coupling capacitance between segment i and j. f ij : switching activities between i and j. Len ij : coupling length. Dist ij : coupling distance.  and  : technology dependent constants.

4 4 Coupling induced delay Delay from CC in Elmore delay model Same amount of coupling leads to different delay depending on coupling location. Most of previous works on layer/track assignment consider crosstalk only, not its impact on timing. [ThakurISCAS95’] [KayISPD00’] a non-critical sink critical sink b Extra delay from CC to the critical sink i j s

5 5 Antenna effect Occurs during manufacturing Conductor layers fabricated from lowest layer to highest layer. Conductor layers, connected only to the gate oxide, called antenna. Risk of gate damage is proportional to the antenna size. Sink 1 Diffusion Sink 2 Antenna violation

6 6 Antenna avoidance methods Diode insertion Add protection diode to gate in case of antenna violation. [ChenISQED00’] [HuangTCAD04’] Jumper insertion Break long antenna by switching wire to the top layer and switch back immediately. [HoISPD04’] Layer assignment Reduce antenna length by layer assignment. [ShirotaCICC98’] [ChenISDFT00’]

7 7 Jumper insertion vs. layer assignment Each jumper costs two vias and a short segment on the top layer. Diffusion Gate Diffusion Gate Diffusion Gate Jumper insertion Antenna violation Layer assignment

8 8 Layer assignment problem formulation Given Global routing solution. Required Arrival Time (RAT) for each sink. Via constraints on the boundaries of two adjacent GRCs. (Global Routing Cells) Goal Maximize the minimum slack among all sinks considering coupling. Number of antenna violations is minimized. Via constraints are satisfied.

9 9 Probabilistic coupling model A routing region r with n uniformly spaced tracks and k wire segments. C r : probabilistic coupling capacitance for a target wire i in r. Cr? ? target wire i other wire Routing region r

10 10 Improved probabilistic model Linear model: a totally random model. Improved model: suitable for a track/detailed router with coupling avoidance. If k < n/2, enough empty tracks to separate signal nets. If k > n/2, adjacent empty tracks are disallowed, otherwise waste of empty tracks. C r =0

11 11 Derivation of the probabilistic model  k,n,1 : number of permutations target wire has one adjacent wire.  k,n,2 : number of permutations target wire has two adjacent wires.  k,n : total number of permutations. Each of  k,n,1,  k,n,2 and  k,n limits to the cases that no two empty tracks are adjacent to each other. otherwise if

12 12 Derivation of  k,n Empty tracks can only be inserted into limited “slots” to avoid their adjacency. After empty tracks are inserted, perform permutation on the wires.  k,n = a wire potential slot for empty tracks  k,n : total # of permutations with no adjacent empty tracks.

13 13 Derivation of  k,n,1 Target wire is not on boundary target wire i other wire empty track bundle potential position for empty tracks  k,n,1 – not_on_boundary =  k,n,1 : total # of permutations target wire has one neighboring wire.

14 14 Derivation of  k,n,1 Target wire is on boundary  k,n,1 =  k,n,1 - not_on_boudary +  k,n,1 - on_boudary target wire i other wire empty track bundle potential position for empty tracks  k,n,1 –on_boundary =  k,n,1 : total # of permutations target wire has one neighboring wire.

15 15 Derivation of  k,n,2 target wire i other wire bundle potential position for empty tracks  k,n,2 =  k,n,2 : total # of permutations target wire has two neighboring wires.

16 16 Comparison of linear model and improved model Comparison of the improved probabilistic model with a linear model [BecerSLIP02] when k =0 ~ 30 and n=30.

17 17 Antenna avoidance through layer assignment Separators : segments that surround an antenna. If separators are limited on the top metal layer (L top ), antenna problem becomes a tree partitioning problem. Metal 1 Metal 2 Metal 3 Metal 4 Sink v Antenna for v “don’t care” region for v

18 18 Tree partitioning for antenna avoidance (TPAA) Find the minimum number of separators such that the size of each resulting sub-tree (containing sinks) is less than A max (Maximum allowed antenna size). Example: TsTsTsTs WT s Ts W(T s ): total length of tree Ts separators

19 19 Linear optimal tree partitioning algorithm An bottom-up approach, adapted from [KunduSIAM77’], each node in the tree processed at most once. At each node u, if W(T u ) > A max, remove minimum number of separators in T u (assign to L top ), such that the resulting W(T u )  A max. A O(n) SPLIT technique to find minimum separators. 1111 11 A max =5 WT u T u W(T u ): total length of tree T u

20 20 Constrained tree partitioning Each metal layer has a preferred routing direction (horizontal or vertical)  not every segment can be assigned to L top. Feasible branch: root edge of a branch can be assigned to L top. Define B MF (u) : maximal feasible branches for T u. Apply tree partitioning on B MF (u) with A max,reduced. A max,reduced =A max - ∑ Weight( infeasible edge separating B MF (u)) u a b d c e 2 1 A max =30 A max,reduced =27 infeasible edge

21 21 Tree partitioning based optimal jumper insertion Similar techniques can be applied to jumper insertions. Time complexity is O(n) and can be applied to the work of [HoISPD04]. 1111 11 A max =5

22 22 Layer assignment heuristic Consider both coupling induced delay and antenna effects. Proceeds in a panel by panel order. Within a panel, most congested region is processed first. Global cell processing order

23 23 Layer assignment heuristic Within each global cell - an MILP problem, we provide a simple heuristic: 1. Assign antenna-critical segments to L top. 2. Sort non-critical segments in non-increasing order of min timing slacks. 3. Partition the non-critical segments to layers  min slack is maximized. Coupling estimated with the probabilistic model. 4. Enforce via constraints. 5. Update slacks for each segment (net) in this cell.

24 24 Layer assignment example Layer assignment example on one global cell. Layer 0 Layer 1 Layer 2 Layer 3 300ps250ps100ps20ps100ps 240ps230ps50ps20ps100ps antenna critical Timing slacks before LA Timing slacks after LA

25 25 Benchmark circuits ISPD98/IBM circuits [AlpertISPD98]. Circuit#GRC#nets#tracks verti panel #tracks hori panel ibm0164×648.8K10 ibm0280×6415.7K2218 ibm0380×6414.6K1514 ibm0496×6417.9K1917 ibm05128×6419.3K3432 ibm06128×6421.9K1815 ibm07192×6429.0K2321 ibm08192×6436.3K2218 ibm09256×6441.6K1814 ibm10256×12843.7K2320 ibm11256×12850.0K1312 ibm12256×12851.6K1815 ibm13256×12859.4K1312

26 26 Benchmark circuit Placement by Dragon [WangICCAD00]. Global routing by a rip-up and re-route router. Our method is compared with three other methods: Method 1: consider only total coupling capacitance. Method 2: coupling capacitance estimated by a trial track/layer assignment method. Method 3: coupling capacitance is estimated using the linear model. Results are validated by a timing-driven track router.

27 27 Experimental results - timing

28 28 Experimental results – Antenna violations LA: Layer Assignment without Antenna Avoidance. LAAA: Layer Assignment with Antenna Avoidance.

29 29 Experimental results – via violations JI : Jumper Insertion.

30 30 Experimental result - CPU CPU time is similar for all methods

31 31 Conclusion An improved probabilistic crosstalk model is proposed to fit for a coupling-aware timing- driven track/detailed router. Antenna avoidance through tree partitioning. Experimental results showed : significant via reductions compare to jumper insertions. timing improvement using the improved probabilistic model. Thank you!

32 32

33 33 SPLIT example A sub-tree T u has 5 branches and A max =24. W(T u )=28. median-find-and-half : Find median, then halve. SPLIT({6,2,9,7,4},24) = SPLIT ({9,7},12)={9} 22233 2225 22 1 TuTu


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