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The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB

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Presentation on theme: "The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB"— Presentation transcript:

1 The Devices Digital Integrated Circuit Design Andrea Bonfanti DEIB
EE141 Digital Integrated Circuit Design Andrea Bonfanti DEIB Via Golgi 40, Milano The Devices

2 EE141 Aims of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Analysis of secondary and deep-sub-micron effects Future trends

3 The Diode Mostly occurring as parasitic element in Digital ICs n p B A
EE141 The Diode n p B A SiO 2 Al Cross-section of pn -junction in an IC process One-dimensional representation diode symbol Mostly occurring as parasitic element in Digital ICs

4 EE141 Depletion Region

5 EE141 Diode Current

6 EE141 Forward Bias Typically avoided in Digital ICs

7 Reverse Bias The Dominant Operation Mode

8 Models for Manual Analysis

9 Junction Capacitance

10 Diffusion Capacitance

11 Secondary Effects Avalanche Breakdown 0.1 ) A ( I –0.1 –25.0 –15.0
I D –0.1 –25.0 –15.0 –5.0 5.0 V (V) D Avalanche Breakdown

12 Diode Model

13 SPICE Parameters

14 What is a Transistor? A Switch! |V GS | An MOS Transistor

15 The MOS Transistor Polysilicon Aluminum

16 MOS Transistors - Types and Symbols
G G S S NMOS Enhancement NMOS Depletion D D G G B S S NMOS with PMOS Enhancement Bulk Contact

17 Threshold Voltage: Concept

18 The Threshold Voltage

19 The Body Effect

20 Current-Voltage Relations A good ol’ transistor
0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT Quadratic Relationship

21 Transistor in Linear

22 Transistor in Saturation
Pinch-off

23 Current-Voltage Relations Long-Channel Device

24 A model for manual analysis

25 Current-Voltage Relations The Deep-Submicron Era
-4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Early Saturation Linear Relationship

26 Velocity Saturation u ( m / s ) u = 10 x = 1.5 x (V/µm) 5 sat n c
Constant velocity Constant mobility (slope = µ) x c = 1.5 x (V/µm)

27 Perspective I V Long-channel device V = V Short-channel device V V - V
GS DD Short-channel device V V - V V DSAT GS T DS

28 ID versus VGS linear quadratic quadratic Long Channel Short Channel
0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V GS (V) I D (A) 0.5 1 1.5 2 2.5 x 10 -4 V GS (V) I D (A) linear quadratic quadratic Long Channel Short Channel

29 ID versus VDS Resistive Saturation VDS = VGS - VT Long Channel
0.5 1 1.5 2 2.5 3 4 5 6 x 10 -4 V DS (V) I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Resistive Saturation VDS = VGS - VT -4 V DS (V) 0.5 1 1.5 2 2.5 x 10 I D (A) VGS= 2.5 V VGS= 2.0 V VGS= 1.5 V VGS= 1.0 V Long Channel Short Channel

30 A unified model for manual analysis
G B

31 Simple Model versus SPICE
0.5 1 1.5 2 2.5 x 10 -4 Velocity Saturated Linear Saturated VDSAT=VGT VDS=VDSAT VDS=VGT (A) I D V (V) DS

32 A PMOS Transistor Assume all variables negative! -2.5 -2 -1.5 -1 -0.5
-0.8 -0.6 -0.4 -0.2 x 10 -4 V DS (V) I D (A) VGS = -1.0V VGS = -1.5V VGS = -2.0V Assume all variables negative! VGS = -2.5V

33 Transistor Model for Manual Analysis

34 The Transistor as a Switch

35 The Transistor as a Switch

36 The Transistor as a Switch

37 MOS Capacitances Dynamic Behavior

38 Dynamic Behavior of MOS Transistor

39 The Gate Capacitance x L Polysilicon gate Top view Gate-bulk overlap
d L Polysilicon gate Top view Gate-bulk overlap Source n + Drain W t ox n + Cross section L Gate oxide

40 Gate Capacitance Cut-off Resistive Saturation < Most important regions in digital design: saturation and cut-off

41 Gate Capacitance Capacitance as a function of VGS
(with VDS = 0) Capacitance as a function of the degree of saturation

42 Measuring the Gate Cap

43 Diffusion Capacitance
Channel-stop implant N 1 A Side wall Source W N D Bottom x Side wall j Channel L S Substrate N A

44 Junction Capacitance

45 Linearizing the Junction Capacitance
Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest

46 Capacitances in 0.25 mm CMOS process

47 The Sub-Micron MOS Transistor
Threshold Variations Subthreshold Conduction Parasitic Resistances

48 Threshold Variations V V Low V threshold Long-channel threshold VDS L
Threshold as a function of Drain-induced barrier lowering the length (for low V ) (for low L ) DS

49 Sub-Threshold Conduction
0.5 1 1.5 2 2.5 10 -12 -10 -8 -6 -4 -2 V GS (V) I D (A) VT Linear Exponential Quadratic The Slope Factor S is DVGS for ID2/ID1 =10 Typical values for S: mV/decade

50 Sub-Threshold ID vs VGS
VDS from 0 to 0.5V

51 Sub-Threshold ID vs VDS
VGS from 0 to 0.3V

52 Summary of MOSFET Operating Regions
Strong Inversion VGS > VT Linear (Resistive) VDS < VDSAT Saturated (Constant Current) VDS  VDSAT Weak Inversion (Sub-Threshold) VGS  VT Exponential in VGS with linear VDS dependence

53 Parasitic Resistances

54 Latch-up Equivalent model

55 Future Perspectives 25 nm FINFET MOS transistor

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