1. CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 4 Temporal and spatial fluctuations in MOSFETs

2. CMOS Analog Design Using All-Region MOSFET Modeling 2 Noise and mismatch The spontaneous fluctuations over time of the current and voltage inside a device, which are basically related to the discrete nature of electrical charge, are called electrical noise. Time-independent variations between identically designed devices in an integrated circuit due to the spatial fluctuations in the technological parameters and geometries are called mismatch. Mismatch (spatial fluctuation) and noise (temporal fluctuation) are similar phenomena, both depending on process, device dimensions, and bias. Mismatch can be seen as “dc noise”.

3. CMOS Analog Design Using All-Region MOSFET Modeling 3 Types of noise: Thermal noise (a) Norton and (b) Thevenin equivalent circuits of a real (noisy) resistor. The resistor in the equivalent circuits is an ideal (noiseless) resistor. Nyquist formulas k=1.38·10 -23 J/K is the Boltzmann constant and  f is the bandwidth in Hertz over which the noise is measured R + G = 1/R (a)(b)

4. CMOS Analog Design Using All-Region MOSFET Modeling 4 Thermal noise calculation Calculate the rms (root mean square) value of the thermal noise current per Hz 1/2 of a 1 mA/V conductance at T= 300 K. On the other hand, the rms value of the thermal noise voltage per Hz 1/2 is

5. CMOS Analog Design Using All-Region MOSFET Modeling 5 Consistency of noise models A noise model is consistent regarding series or parallel associations if the composition of the noise contributions from the individual series (or parallel) elements is the same as the noise from the series (or parallel) equivalent. The thermal noise model for a resistor given by is consistent The total noise voltage introduced into the circuit can be obtained by composing the individual noise sources or using Nyquist formula to calculate the noise of the equivalent resistor R eq =R 1 +R 2. R1R1 R2R2 + +

6. CMOS Analog Design Using All-Region MOSFET Modeling 6 Shot noise ( vacuum tubes, diodes, and bipolar transistors) Shot noise is associated with the random flow of carriers across a potential barrier. The fluctuation of a current I around its average value I DC Shot noise is given by the Schottky formula as q is the electronic charge and  f is the bandwidth in Hertz The rms value of the shot noise per Hz 1/2 in a p-n junction diode for a 1  A dc current is

7. CMOS Analog Design Using All-Region MOSFET Modeling 7 Flicker (1/f) noise All active devices, and some passive devices such as carbon resistors, present excess noise at low frequencies, which is called flicker noise. Flicker noise occurs when a direct current is flowing: flicker noise can be regarded as produced by a fluctuation in conductance. The power spectral density of flicker noise varies with frequency in the form with K and EF being constants. Since in most cases EF  1, flicker noise is also called 1/f noise.

8. CMOS Analog Design Using All-Region MOSFET Modeling 8 Calculation of flicker noise Assume that EF = 1 and K=10 -20 A 2. Calculate the mean square value of the flicker noise current over a frequency range of (a) [10 Hz, 10 kHz]; (b) [10 Hz, 10 MHz]; (c) [(1 (million year) -1, 1 year -1 ] which leads to the following results a) b) c)

9. CMOS Analog Design Using All-Region MOSFET Modeling 9 Modeling drain current fluctuations - 1 Channel splitting Transistor equivalent circuit yy L W L-y y AA M l : W/y M u : W/(L-y) VDVD VGVG RR

10. CMOS Analog Design Using All-Region MOSFET Modeling 10 Current division Modeling drain current fluctuations - 2

11. CMOS Analog Design Using All-Region MOSFET Modeling 11 MOSFET thermal noise Conductance of a MOSFET channel element Mean-square thermal noise of the channel element Nyquist Mean-square value of the total drain current fluctuation

12. CMOS Analog Design Using All-Region MOSFET Modeling 12 Thermal noise excess factor - 1 For V DS  0, the transistor is equivalent to a resistor and where g ms (=g md ) is the equivalent conductance of the transistor In weak inversion For a saturated transistor (g ms >>g md ) in weak inversion

13. CMOS Analog Design Using All-Region MOSFET Modeling 13 In general, the channel thermal noise is written as  is named the excess noise factor and its value is 2/3 for a long- channel saturated transistor in strong inversion. For a short channel transistor L e and L esat are the electrical channel length in the linear and the saturation regions, respectively. Considering that L esat = L e -  L, where  L is the channel shortening due to CLM, then for short channel transistors it is possible that  >1 due to the CLM effect. Thermal noise excess factor - 2

14. CMOS Analog Design Using All-Region MOSFET Modeling 14 Flicker noise in MOSFETs Spectral density of a simulated waveform obtained superimposing many random telegraph signals with single time constants having values generated according to

15. CMOS Analog Design Using All-Region MOSFET Modeling 15 : effective number of traps/area As for thermal noise, we calculate the mean-square value of the total drain current fluctuation from the local current fluctuation in the channel In terms of inversion levels Flicker (1/f) noise model

16. CMOS Analog Design Using All-Region MOSFET Modeling 16 Dependence of the 1/f noise on bias Flicker NoiseWeak Inversion (i f <1) Strong Inversion (i f >>1) Linear Region (i f  i r ) Saturation Region (i f >>i r )

17. CMOS Analog Design Using All-Region MOSFET Modeling 17 Thermal and 1/f noise 10n100n1µ10µ100µ1m10m 1E-15 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 (N ot =2.6x10 7 cm -2 ) Thermal Noise Simulated (Typ.NMOS model) measured 1/f Noise Simulated (a) Simulated (b) measured S ID /I D 2 Drain Current [A] Normalized flicker and thermal PSD at f=1kHz for saturated NMOS-T (W/L=200/5)

18. CMOS Analog Design Using All-Region MOSFET Modeling 18 Corner frequency Noise corner frequency (frequency at which the PSD of the 1/f noise equals the PSD of the thermal noise) can be expressed in terms of MOSFET transition frequency

19. CMOS Analog Design Using All-Region MOSFET Modeling 19 Systematic and random mismatch Mismatch is the name given to the time-independent differences between identically designed and identically used devices. The performance of most analog, or even digital, circuits relies on the concept of matched behavior between identically designed and used devices. In analog circuits, unwanted differences in the effective value of equally designed components, such as threshold voltage differences of millivolts or less, can critically reduce the performance and/or yield of a circuit. Even for digital circuits, transistor mismatch can lead to propagation delay differences in clock trees, reducing the robustness of the circuit. The shrinkage of the MOSFET dimensions and the reduction in the supply voltage make matching limitations even more important.

20. CMOS Analog Design Using All-Region MOSFET Modeling 20 Global manufacturing variations GLOBAL variation  total variation of a parameter over a chip, a wafer (a batch) caused by equipment variations & spatial drift, e. g. Dimensional errors (photo-mask sizes, lens aberrations) Photo-resist thickness variations Mechanical strain variation Because GLOBAL variations are correlated across die, they are minimized by design tricks: common centroid components distance reduction between identically designed pairs same orientation, etc.

21. CMOS Analog Design Using All-Region MOSFET Modeling 21 Random local variations LOCAL variation  variation in a component with respect to an identical adjacent component, caused by atomistic stochastic effects ion implantation, dopant diffusion and clustering Interface states, fixed charges edge roughness, poly-Si grain effects Simulation: generate random mismatch that depends on dimensions, process parameters, and bias. Designers must understand the limitations imposed by LOCAL variations on performance.

22. CMOS Analog Design Using All-Region MOSFET Modeling 22 Pelgrom’s model of mismatch - 1 number of atoms per unit volume in silicon is N Si =5·10 22 cm -3 probability p of having an acceptor atom in the place of a silicon atom number N of crystal atoms in the depletion region under the gate fluctuation in the number of acceptor atoms under the gate of an n-channel transistor (binomial distribution) since p<<1(Poisson distribution) W L xdxd drain source

23. CMOS Analog Design Using All-Region MOSFET Modeling 23 In most applications: standard deviation of the difference between the threshold voltages of two identical transistors (  V T0 =V T1 -V T2 ) Pelgrom’s model of mismatch - 2

24. CMOS Analog Design Using All-Region MOSFET Modeling 24 Pelgrom’s model of mismatch - 3 The standard deviation of the n-channel MOSFET threshold voltage vs. the inverse square root of the gate area for a.18  m process

25. CMOS Analog Design Using All-Region MOSFET Modeling 25 VTO matching coefficient vs. process The threshold-voltage matching coefficient over process generations

26. CMOS Analog Design Using All-Region MOSFET Modeling 26 Number fluctuation mismatch model - 1 V GB depletion charge p-substrate 0 y yy inversion charge inversion charge Cross section of an MOS transistor showing the (greatly exaggerated) fluctuations in both inversion and depletion charge densities due to local dopant fluctuations

27. CMOS Analog Design Using All-Region MOSFET Modeling 27 N oi : effective number of impurities per unit area of gate Assumptions and/or approximations: The capacitive model of the MOS transistor, assuming the depletion capacitance to be dependent on the gate voltage only and the inversion capacitance to be proportional to the inversion charge density; The fluctuation of the impurity concentration in the depletion layer as the main source of mismatch; Poisson distribution of impurity atoms; Uncorrelated local impurity fluctuations; Number fluctuation mismatch model - 2

28. CMOS Analog Design Using All-Region MOSFET Modeling 28 Mismatch dependence on inversion level - 1 In terms of inversion levels where _______________________ For long channel MOSFET

29. CMOS Analog Design Using All-Region MOSFET Modeling 29 Weak inversion (i f <<1) Strong inversion (i f >>1) Linear region (i f  i r ) Saturation region (i f >>i r ) Mismatch dependence on inversion level - 2

30. CMOS Analog Design Using All-Region MOSFET Modeling 30 Mismatch model including I S fluctuations One can include the random errors due to the specific sheet current A ISH is the parameter which accounts for mismatch in I SH. For high inversion levels, mismatch levels out at a minimum value determined by A ISH A ISH values are of the order of 1 %-  m

31. CMOS Analog Design Using All-Region MOSFET Modeling 31 Mismatch: Experimental results – 1 Test circuit MiMi M REF IDID IBIB VBVB VGVG VDVD Saturation level dependence Measured: —; Model: --- Test chip: 24 NMOS transistors (W=30  m, L= 1.2  m) in the ES2 1.2  m CMOS DLM process

32. CMOS Analog Design Using All-Region MOSFET Modeling 32 Dependence on inversion level Linear:  (V DS =50mV); Saturation:  (V DS =1V) regions. —; Model Mismatch: Experimental results – 2