1. VLSI Design Lecture 2: Basic Fabrication Steps and Layout Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture notes

2. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 2 of 50 Outline n How to make a transistor or a gate  Cross-section  Top view (masks)  Fabrication process n Layout n Design rules n Standard cell layouts n Stick Diagrams

3. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 3 of 50 Our technology n We will study a generic 180 nm technology (SCMOS rules).  Assume 1.2V supply voltage. n Parameters are typical values. n Parameter sets/Spice models are often available for 180 nm, harder to find for 90 nm.

4. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 4 of 50 Fabrication services n Educational services:  U.S.: MOSIS (has defined SCMOS rules)  EC: EuroPractice  Taiwan: CIC  Japan: VDEC n Foundry = fabrication line for hire.  Foundries are major source of fab capacity today.

5. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 5 of 50 Silicon Lattice n Transistors are built on a silicon substrate n Silicon is a Group IV material n Forms crystal lattice with bonds to four neighbors

6. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 6 of 50 Dopants n Silicon is a semiconductor n Pure silicon has no free carriers and conducts poorly n Adding dopants increases the conductivity n Group V (Arsenic, Phosphorus) : extra electron (n-type) n Group III (Boron) : missing electron, called hole (p-type)

7. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 7 of 50 p-n Junctions n A junction between p-type and n-type semiconductor forms a diode. n Current flows only in one direction N-Diff P-Diff anodecathode

8. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 8 of 50 Fabrication processes n IC built on silicon substrate:  some structures diffused into substrate;  other structures built on top of substrate. n Substrate regions are doped with n-type and p-type impurities. (n+ = heavily doped) n Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal). n Silicon dioxide (SiO 2 ) is insulator.

9. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 9 of 50 CMOS Fabrication n CMOS transistors are fabricated on silicon wafer n Lithography process similar to printing press n On each step, different materials are deposited or etched n Easiest to understand by viewing both top and cross- section of wafer in a simplified manufacturing process

10. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 10 of 50 CMOS Inverter

11. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 11 of 50 Inverter Cross-section n Typically use p-type substrate for nMOS transistors n Requires n-well for body of pMOS transistors

12. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 12 of 50 Well and Substrate Taps n Substrate must be tied to GND and n-well to V DD n Metal to lightly-doped semiconductor forms poor connection called Shottky Diode n Use heavily doped well and substrate contacts / taps

13. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 13 of 50 Inverter Mask Set n Transistors and wires are defined by masks n Cross-section taken along dashed line

14. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 14 of 50 Detailed Mask Views n Six masks  n-well  Polysilicon  n+ diffusion  p+ diffusion  Contact  Metal

15. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 15 of 50 Fabrication Steps n Start with blank wafer n Build inverter from the bottom up n First step will be to form the n-well  Cover wafer with protective layer of SiO 2 (oxide)  Remove layer where n-well should be built  Implant or diffuse n dopants into exposed wafer  Strip off SiO 2

16. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 16 of 50 Oxidation n Grow SiO 2 on top of Si wafer  900 – 1200 C with H 2 O or O 2 in oxidation furnace

17. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 17 of 50 Photoresist n Spin on photoresist  Photoresist is a light-sensitive organic polymer  Softens where exposed to light

18. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 18 of 50 Lithography n Expose photoresist through n-well mask n Strip off exposed photoresist

19. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 19 of 50 Etch n Etch oxide with hydrofluoric acid (HF)  Seeps through skin and eats bone; nasty stuff!!! n Only attacks oxide where resist has been exposed

20. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 20 of 50 Strip Photoresist n Strip off remaining photoresist  Use mixture of acids called piranah etch n Necessary so resist doesn’t melt in next step

21. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 21 of 50 n-well n n-well is formed with diffusion or ion implantation n Diffusion  Place wafer in furnace with arsenic gas  Heat until As atoms diffuse into exposed Si n Ion Implanatation  Blast wafer with beam of As ions  Ions blocked by SiO 2, only enter exposed Si

22. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 22 of 50 Strip Oxide n Strip off the remaining oxide using HF n Back to bare wafer with n-well n Subsequent steps involve similar series of steps

23. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 23 of 50 Polysilicon n Deposit very thin layer of gate oxide  < 20 Å (6-7 atomic layers) n Chemical Vapor Deposition (CVD) of silicon layer  Place wafer in furnace with Silane gas (SiH 4 )  Forms many small crystals called polysilicon  Heavily doped to be good conductor

24. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 24 of 50 Polysilicon Patterning n Use same lithography process to pattern polysilicon

25. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 25 of 50 Self-Aligned Process n Use oxide and masking to expose where n+ dopants should be diffused or implanted n N-diffusion forms nMOS source, drain, and n-well contact

26. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 26 of 50 N-diffusion n Pattern oxide and form n+ regions n Self-aligned process where gate blocks diffusion n Polysilicon is better than metal for self-aligned gates because it doesn’t melt during later processing

27. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 27 of 50 N-diffusion cont. n Historically dopants were diffused n Usually ion implantation today n But regions are still called diffusion

28. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 28 of 50 N-diffusion cont. n Strip off oxide to complete patterning step

29. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 29 of 50 P-Diffusion n Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact

30. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 30 of 50 Contacts n Now we need to wire together the devices n Cover chip with thick field oxide n Etch oxide where contact cuts are needed

31. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 31 of 50 Metalization n Sputter on aluminum over whole wafer n Pattern to remove excess metal, leaving wires

32. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 32 of 32 Simple cross section substrate n+ p+ substrate metal1 poly SiO 2 metal2 metal3 transistor via

33. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 33 of 32 Photolithography Mask patterns are put on wafer using photo-sensitive material:

34. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 34 of 32 Process steps n First place tubs (wells) to provide properly-doped substrate for n-type, p-type transistors. a twin-tub process: p-tubn-tub substrate

35. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 35 of 32 Process steps, cont’d. Pattern polysilicon before diffusion regions: p-tubn-tub poly gate oxide

36. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 36 of 32 Process steps, cont’d Add diffusions, performing self-masking: p-tubn-tub poly n+ p+

37. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 37 of 32 Process steps, cont’d Start adding metal layers: p-tubn-tub poly n+ p+ metal 1 vias

38. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 38 of 32 Transistor structure n-type transistor:

39. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 39 of 32 0.25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

40. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 40 of 32 Transistor layout n-type (tubs may vary): w L

41. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 41 of 32 NMOS Transistor n Four terminals: gate, source, drain, body n Gate – oxide – body stack looks like a capacitor –Gate and body are conductors –SiO 2 (oxide) is a very good insulator –Called metal – oxide – semiconductor (MOS) capacitor »Even though gate is no longer made of metal

42. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 42 of 32 NMOS Operation n Body is commonly tied to ground (0 V) n When the gate is at a low voltage: –P-type body is at low voltage –Source-body and drain-body diodes are OFF –No current flows, transistor is OFF

43. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 43 of 32 NMOS Operation (cont’d.) n When the gate is at a high voltage: –Positive charge on gate of MOS capacitor –Negative charge attracted to body –Inverts a channel under gate to n-type –Now current can flow through n-type silicon from source through channel to drain, transistor is ON

44. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 44 of 32 PMOS Transistor n Similar, but doping and voltages reversed –Body tied to high voltage (V DD ) –Gate low: transistor ON –Gate high: transistor OFF –Bubble indicates inverted behavior

45. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 45 of 32 Drain current characteristics

46. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 46 of 32 Drain current n Linear region (V ds < V gs - V t ): –I d = k’ (W/L)[(V gs - V t )V ds - 0.5 V ds 2 ] n Saturation region (V ds ≥ V gs - V t ): –I d = 0.5k’ (W/L)(V gs - V t ) 2

47. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 47 of 32 180 nm transconductances Typical values: n n-type: –k n ’ = 170  A/V 2 –V tn = 0.5 V n p-type: –k p ’ = 30  A/V 2 –V tp = -0.5 V

48. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 48 of 32 Current through a transistor Use 180 nm parameters. Let W/L = 3/2. Measure at boundary between linear and saturation regions. n V gs = 0.7V: I d = 0.5k’(W/L)(V gs -V t ) 2 = 0.5(170  A/V 2 )(3/2)(0.7-0.5) 2 = 5.1  A n V gs = 1.2V: I d = 62  A

49. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 49 of 32 Basic transistor parasitics n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance.

50. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 50 of 32 Basic transistor parasitics, cont’d n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. –C gs = C ol W n Gate/bulk overlap capacitance.

51. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 51 of 32 Latch-up n CMOS ICs have parastic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low- resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

52. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 52 of 32 Parasitic SCR structure n There exist parasitic bipolar transistors (pnp and npn) in a CMOS structure. n Additionally, the well and substrate have resistances R W and R S, respectively. n+ p substrate p+ A Y GND V DD n+p+ substrate tap well tap n+p+ n well R sub R well V sub V well Twin tub n tub

53. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 53 of 32 Parasitic SCR circuitI-V behavior

54. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 54 of 32 Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection.

55. Modern VLSI Design 4e: Chapter 2 Sharif University of Technology Slide 55 of 32 Tub tie layout metal (V DD ) p-tub p+