1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Color space transformation Phase 4 Heiko Westphal> 12.01.2012 Institute MD, University of Rostock

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Workflow Optimization of Synopsys synthesis parameters  Better Synthesis result: frequency: 200 Mhz (old 150 Mhz) leakage power: 272 nW (old 305 nW)  improvement of synthesis metric to 0.880 pJ (old 1.3169 pJ) Slide 2

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Chip Layout First try: maximum chip size (500*500): pretty bad result (138 Mhz) Parameter optimization: different sizes/densities: 7% - 98% different aspect ratios: 0.97 - 2 Best result at ration h/w 1.3275 with density 89.9%: 151 Mhz  Metric: 1.17 pJ Slide 3

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Design Optimization On netlist much more leakage power less frequency  failed Optimize Design Parameters: Low Leakage Power Effort and Low Timing Effort Successful: Leakage power decreased to 169.34 nW But: frequency went down to 101 Mhz too  still bit better metric: 1.074 pJ Slide 4

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Timing (T min / f max )9.882 ns | 101.19 Mhz Power (P dyn / P leak )234.6464 µW | 169.3482 nW E_avg0.249936 t OP 406,38 µs Benchmark 1.074 pJ Core size20210.463 µm² Core utilization89.56 % Slide 5

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Remark on results Why did frequency decreased from synthesis to layout? Synthesis: 200 Mhz Layout: 150 Mhz At same leakage power Reason: synthesis doesn’t know wire length  Ignores delay of wires between units Example: one of the critical paths Slide 6

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 7