1. Design of Binary Arithmetic Circuits Experiment 7

2. Lab Report Comments: VHDL code should be easily readableVHDL code should be easily readable –Proper indentation –Commented –Title banner (names, description, etc) –No line wrap! –Self commented names Include block diagramsInclude block diagrams –Especially if multiple devices interconnected

3. Lab Report Comments: Circuit Diagrams: ALWAYS INCLUDE ! –Titled with a descriptive name for the circuit –Brief verbal description of the circuit's function / purpose (what does it do?) –Circuit schematic and/or block diagram Include all input/output signalsInclude all input/output signals –When circuits are implemented in VHDL, signal names on schematics should match signal names used in your VHDL code Include all input/output signals sources / destinations on the Development Board (switches, LEDs, etc.)Include all input/output signals sources / destinations on the Development Board (switches, LEDs, etc.) If combining multiple modules, show each module and the interconnectionsIf combining multiple modules, show each module and the interconnections –Not just 1 big “black box” for the whole thing.

4. Modular Design & Design Reuse Best to “reuse” a previously-designed, tested, verified VHDL module with as little change as possible –…or NONE, if possible! –Changes negate the benefits of having a “proven, working” design Ex: Rewriting the BCD-7seg in Exp 6 to use only 3-bit inputs (to match Priority Enc output) was not the “best” solution This week, we will use a more powerful implementation of “Modular Design”…….. VHDL Structural Modeling

5. VHDL Structural Modeling Reflects modern digital circuit design practice Supports preferred digital design approach Hierarchical (Top-Down) Design

6. VHDL Structural Modeling Hierarchical (Top-Down) Design Digital Alarm System BCD-7 Seg Decoder Priority Encoder 4-bit Digital Comparator Alarm Controller FSM AND_2 (AND gate) NOR_2 (NOR gate) 1-bit Digital Comparator D Flip-Flop (This is an Example of Multi-level Hierarchical Design. It is NOT necessarily how YOU should complete Exp 9.)

7. VHDL Structural Modeling Reflects modern digital circuit design practice Supports preferred digital design approach: Hierarchical (Top-Down) Design Leverages software design techniques Supports readability, understandability, and reuse of code Allows for easy scalability of design Allows for the use of library-based modules

8. Instructional Objectives: To use concurrent VHDL statements in the design of arithmetic circuitsTo use concurrent VHDL statements in the design of arithmetic circuits –Half Adder –Full Adder Use “Structural Modeling” in VHDLUse “Structural Modeling” in VHDL –4-bit Ripple Carry Adder –Using Half Adder & Full Adder as “Components” –“Top Module” in same “Project” as Half Adder & Full Adder To design a 4-bit Comparator (need for Alarm System)To design a 4-bit Comparator (need for Alarm System) –Any VHDL Model style (architecture) you like (Hint: Probably NOT structural!)(Hint: Probably NOT structural!)

9. 1-Bit Binary Addition To Add Two Single-Bit Binary Numbers: A0A0B0B0 Sum S0 Carry CO ut 0000 0110 1010 1101 A0B0A0B0 A0B0A0B0 1-Bit Binary Adder Half Adder Half Adder A i B i CO i S i A 0 B 0 S0S0 CO 0

10. Multiple-Bit Binary Addition Alternative Approach: Modular Design Use same approach as manual computation Apply the same basic binary addition rules at each bit position Need to handle “Carry In” for higher bit position additions Modular Approach Design a 1-bit “Full Adder” for 2 numbers + Carry In Reuse the design for each upper bit position A 3 A 2 A 1 A 0 + B 3 B 2 B 1 B 0 CO S 3 CO 2 S 2 CO 1 S 1 CO 0 S 0 A 3-0 + B 3-0 _______________________ CO S 3-0 CI 1 CI 2 CI 3

11. Input VariablesOutputs ABCI n Carry CO ut S um 000 001 010 011 100 101 110 111 1-Bit Binary Full Adder To Add Two 1-Bit Binary Numbers w/Carry In : Input VariablesOutputs ABCI n Carry CO ut S um 00000 00101 01001 01110 100?? 101?? 110?? 111?? Full Adder A i B i C I i CO i S i A B CI S CO

12. 4- Bit Ripple-Carry Adder A 3 A 2 A 1 A 0 + B 3 B 2 B 1 B 0 S 3 S 2 S 1 S 0 Full Adder A i B i CI i CO i S i A 3 B 3 CI 3 S3S3 CO 3 Full Adder A i B i CI i CO i S i A 2 B 2 CI 2 S2S2 CO 2 Full Adder A i B i CI i CO i S i A 1 B 1 CI 1 S1S1 CO 1 Half Adder A i B i CO i S i A 0 B 0 S0S0 CO 0 CI 1 CI 2 CI 3 CO 0 CO 1 CO 2 COut

13. VHDL Concurrent Statement Refresher ARCHITECTURE mad_hatter OF myhalfadder IS BEGIN concurrent statement1; -- half adder sum equation concurrent statement2; -- half adder carry equation END myarch;

14. VHDL Structural Modeling Similar to higher level language programming Example circuit

15. VHDL Code for “Modules”

16. Structural VHDL Code A F B A F B A F B

17. Code3 Code2 Code1 Code0 EQ I3 I2 I1 I0 Key Comparator 4 switches (access code) I7 I6 I5 Y2 I4 Y1 I3 Y0 I2 I1 STROBE I0 Priority Encoder 4 switches (sensors) Connect to ground Break-in Armed OFF/ON_L Alarm B3 B2 AA-AG B1 CATH B0 7-Seg Decoder Alarm Control Digital Alarm System Experiment 7 P3 Preset Secret Code 4-Bit Comparator

18. Given two 4-bit binary numbers, A and B, determine if they are equal. Multiple solutions: –Subtract B from A and test for zero result –Use VHDL operators require special libraries –Use XNOR gates to do a bitwise comparison

19. Experiment 7 Overview P1:Design, test, and implement a Half Adder P2: Design, test, and implement a Full Adder P3:Design and implement a 4-bit Ripple Carry Adder Using Structural Modeling - Behavioral Simulation P4:Design and implement a 4-bit Comparator Save for use in Experiment 9

20. 4-bit sum Of A+B Nexys Development Board Carry out EQUAL AB

21. Place & Route Post-Route Simulation Behavioral Simulation Design Verification Steps Is the basic logic correct? Does the design still work with the actual devices used ( with prop. delays, etc.) ? An important step for “real world” designs!!

22. Testing Strategies We want to create input signal “test vectors” that will: Verify all important functions of our designs are working properly Be THOROUGH….. –Cover as many functions / cases as possible …..AND be EFFICIENT –Use as few test cases (vectors) as possible

23. Testing Strategies Possible Approaches: 1.Test ALL POSSIBLE input combinations (Truth Table) –Thorough!! –Good approach if the number of inputs is small. If not reasonable, then consider: 2.Targeted Functional Testing –What are the important functions to verify? –What is already proven? (reuse)...what is not? –What could have gone wrong in the design that I should check for? –How can we test each issue as efficiently as possible? If it ain’t too bad,…Why not???

24. Then,… BRAINSTORM

25. Testing the Half & Full Adders Full Adder A i B i CI i CO i S i A 1 B 1 CI 1 S1S1 CO 1 Half Adder A i B i CO i S i A 0 B 0 S0S0 CO 0 How would you suggest testing these two devices? What method / test vectors would you choose?

26. Testing the Ripple-Carry Adder Full Adder A i B i CI i CO i S i CI 3 S3S3 CO 3 Full Adder A i B i CI i CO i S i A 2 B 2 CI 2 S2S2 CO 2 Full Adder A i B i CI i CO i S i A 1 B 1 CI 1 S1S1 CO 1 Half Adder A i B i CO i S i A 0 B 0 S0S0 CO 0 COut A 3 B 3 How many input signals? How many Test Vectors to test ALL CASES? 4 (A) + 4 (B) = 8 2 8 = 256 Good Luck!!

27. Testing the Ripple-Carry Adder Full Adder A i B i CI i CO i S i CI 3 S3S3 CO 3 Full Adder A i B i CI i CO i S i A 2 B 2 CI 2 S2S2 CO 2 Full Adder A i B i CI i CO i S i A 1 B 1 CI 1 S1S1 CO 1 Half Adder A i B i CO i S i A 0 B 0 S0S0 CO 0 COut A 3 B 3 If you’ve already proven that the Half Adder & Full Adder designs are OK,… What other “features” of the RCA do you need to verify? What “mistakes” could you have made in the structural design that you should check for?

28. 4- Bit Comparator ABAB 4-bit Digital Comparator = 1 : if A = B = 0 : if A \= B 4 4 EQUAL Verification Testing of the How might we approach “efficiently” testing this device?

29. Ideas for testing HA & FA: Test all RCA: –Inputs connected right? A3->InA3, B3->InB3, etc Test each bit position (i): A i =1, A rest =0, B=0000; generates SUMi=1, no carries –Example: Bit 1: A = 0010, B = 0000, Sum = 0010? CarryOut=0? Test each bit position (i): B i =1, B rest =0, A=0000; generates SUMi=1, no carries –Example: Bit 2: A = 0000, B = 0100, Sum = 0100? CarryOut=0? –Carry ripple connected right? Generate carry from LSB all way to carryout A=1111, B=0001 Generate sum with no carries 0101 + 1010 Comparator EQUAL= 1 For All bits equal with 1’s A=1111, B=1111 EQUAL= 1 For All bits equal with 0’s A=0000, B=0000 EQUAL= 1 For All bits equal alternating bits 0101 0101 1010 1010 EQUAL= 0 For All Equal except 1 bit: 0001 0000 1110 1111 0010 00001101 1111 0100 00001011 1111 1000 00000111 1111