1. XIAOXI XU AND CHENG-CHEW LIM, SENIOR MEMBER, IEEE IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 6, JUNE 2010 Modeling Interrupts for Software-Based System-on-Chip Verification : :0115924

2. Abstract The interrupt mechanism in a system-on-chip (SoC) joins the SoCs hardware and software behaviors. We model interrupts as logical rather than physical events and accordingly provides guidelines to compose software components including interrupt-service-routines. As a benefit, classical in deterministic behaviors (due to the parallelism) in the software domain, such as preemption and nesting, can be constructed as early as raw hardware components are being integrated. In effect, while the interrupt mechanism itself is under rigorous stress, it is simultaneously driving the exercise of the entire SoC. This effect can be observed through software profiling at the hardware integration stage.

3. Introduction and Background When HW components are being integrated into a system and serviced and stimulated by software, it is problematic to interpret interrupts as pure HW phenomena. Many methods emphasize the hardware side of verification, usually focusing on the interference between the processors interrupt-response behaviors and its pipeline behaviors. But these approaches ignore emergent properties (such as interrupt service latency and turn-around time) and interaction glitches (which are hard to anticipate, such as those in preemption, nesting and reentrance) rising from HW-SW interaction. This paper elaborates how to model interrupts with their interrupt-service- routines (ISRs) as events associated with interactions-object rather than with HW components. The contributions of this paper include: 1) composing ISRs in a general form to support parallelism management (control); and 2) proposing preemption-based coverages to measure the parallelism (observation).

4. Interrupt Modeling

5. Test-Program Role 1: Interrupt service routines (ISRs) cooperating with raw hardware to fulfill their intended functionalities. Role 2: Some software components, called soft transfers, stressing hardware to expose any potential problems. Role 3: One scheduling component managing parallelism among transfers(TRG method).

6. Report

7. SOC 1 2 3 4 5 6 CPU FPGA->VGA CPU FPGA->VGA CANBUS 1ms,,,,,,

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