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The integrated Development of Embedded linux and SOC IP
吳奇峰 新華電腦股份有限公司 應用工程師
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Topics SOC 系統發展流程 FPGA 發展工具 SOPC Builder 流程
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H/W & S/W adoption trade-off by verification
SOC 嵌入式系統開發流程 System Requirement Design Specification Components, IP Sourcing H/W & S/W partitioning H/W Design synthesis S/W Design IC Tool Compiler ICE CO-simulation Debugger OS H/W & S/W adoption trade-off by verification Product
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Creator Motherboard Memory: Communication: Human-Machine Interface:
2M Bytes Flash Memory、16M Bytes SDRAM 、 EEPROM Communication: UART、Ethernet、USB 1.1 、I2C Human-Machine Interface: Codec 、CMOS Camera、Ｋeypad、LED、7-Seg、 DIP Switch、LCD Master and Slave Bus for daughter board Changeable: Create S3C4510 (ARM7TDMI) Create ARM920T-S3C2410 Create ARM922T-EPXA1 (for SOPC) Create FPGA-EP1C6 Create FPGA-XC2S Create TIDSP-5502
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Create FPGA-EP1C6 FPGA: EP1C6;BQ240(5980LEs) Codec: Stereo out
Microphone in 8-Bit serial I/O ADC with 2-channel multiplexed SRAM:128K*8-Bit 7-Seg LED 9 LED Lamps 4-Way DIP Swich 1 Tag Switch 1 DC Buzzer for tone generation
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Create FPGA-EP1C6 PS2 Connector
Build-in Altera ByteBlasterMV Parallel Port download cable header circuit Extension connector 27 pins for memory interface 50 pins for user definable I/O One 8-Bit ADC input 4 Pins Codec I/O 5V DC output Slave Bus Communicate with Master Bus site CPU Keypad Switch 、 UART interface
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Create FPGA-EP1C6 Block Diagram
Config CKT SRAM PC DIP-SW ICE LED 7-Seg Cyclone EP1C6 FPGA PS2 Creator BUS (Slave Bus) Buzzer Clock A2D VR MIC STEREO CODEC Buffer Regulator Expansion I/O
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Create FPGA-XC2S FPGA: XC2S,PQ208(200K gate counts) Codec:
16-Bit, 26-KSPS,TLV320AIC12 Built-in Microphone 8-Bit serial I/O ADC with 2-channel multiplexer SRAM: 128K*8Bit 7-Seg LED 9 LED Lamps 4-Way DIP Switch 1 Tag Switch
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Create FPGA-XC2S PS2 Connector
Build-in Xilinx download cable header circuit Extension connector 27 pins for memory interface 10 pins for user definable I/O One 8-Bit ADC input One 16-Bit Codec Aux input 5V DC output Slave Bus Communicate with Master Bus site CPU Keypad Switch UART interface
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Create FPGA-XC2S Block Diagram
Config CKT SRAM PC DIP-SW ICE LED 7-Seg Spartan-II FPGA PS2 Creator BUS (Slave Bus) Buzzer Clock A2D VR MIC STEREO CODEC Buffer Regulator Expansion I/O
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Creator Bus Communication
Master Bus (CPU) Slave Bus Address Bus UART Data Bus Key Pad S3C4510 (ARM7TDMI) ARM920T S3C2410 I/O ARM922T EPXA1 (for SOPC) Power IRQ DMA FPGA Config. Controls TI DSP 5502 Creator Mother Board
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Create ARM922T-EPXA1 CPU:EPXA1F484C3 ARM922T Core 100K Gate Count FPGA
10/100 Ethernet Master Bus Two Clock Sources 8M-Byte Flash Memory 32M-Byte SDRAM 8 LED Lamps 4-Way DIP switch 1 Tag Switch
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Create ARM922T-EPXA1 4 extension connectors for wire wrap board or special hardware module Totally 118 I/O pins 3 Clock Output pins 2 Fast input pins 5V DC Output Header for ARM ICE JTAG Connector Header for Altera Byte Blaster MV download cable Running Linux,Linux open source codes provided
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Create ARM922T-EPXA1 Board Architecture
EPXA1 Control ARM JTAG Extension I/O PLD JTAG EPXA1 PLD LED/DIP SW/TAG SW POWER EPXA1 ARM-Strip SDRAM Flash Ethernet Clocks Create ARM922T-EPXA1 Master Bus JH1 JH2 Creator Motherboard
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Excalibur ARM Configuration
SDRAM Flash ROM SRAM SDRAM Controller Expansion Bus Interface (EBI) UART ARM922T Processor Interrupt Controller Watchdog Timer AHB1 Configuration Logic Master AHB 1-2 Bridge Configuration Register AHB2 Single--Port SRAM Phase- Locked Loop (PLL) Reset Module Timer PLD-to-Stripe Bridge Dual-Port SRAM Stripe-to-PLD Bridge AHB AHB Excalibur Hard Processor FPGA Logic Programmable Logic Slave Peripheral Programmable Logic Slave Peripheral Programmable Logic Master Peripheral Programmable Logic Module Programmable Logic Module IP External Devices AHB: AMBA™ High-Performance Bus
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Intellectual Property Intellectual Property
SOPC Builder Flow Intellectual Property Intellectual Property SOPC Builder GUI Processor Library Configure Processor Custom Instructions Peripheral Library Select & Configure Peripherals, IP IP Modules EDIF Netlist HDL Source Files Testbench Synthesis & Fitter User Design Other IP Blocks Hardware Development Quartus II Connect Blocks C Header files Custom Library Peripheral Drivers GNUPro Compiler IAR ARM Compiler uClinux/Linux Software Development User Code Libraries OS(Kernel…….. Software Tools Generate Hardware Configuration File Executable Code Verification & Debug JTAG Microtime Carrier ICE Embedded processors require both hardware design and software design. 1. SOPC Builder walks the user through the process of defining a custom Nios system 2. SOPC Builder then Generates a hardware flow for synthesizing the Nios system and combining it with the user’s custom logic. 3. SOPC Builder also generates a software flow: An environment for the GNUPro Toolkit with all the software components required to compile software for this custom hardware. 4. Hardware and software prototype and debug is very easy, by downloading hardware and software images to the Nios Development Board. Domingo Debugger For uClinux/Linux CREAE ARM922T EXPA1
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