1. 1 Lab7 Design and Implementation

2. 2 Design Example : Parity checker

3. 3 Computer to Spartan-6 USB Port Spartan-6 PC

4. 4 DIP SWITCHES & LEDs DIP SWITCH LED

5. 5 Power to Board 變壓 整流器 AC 110V DC 5V

6. 6 Create a New Project

7. 7 Enter a Name and Location for the Project 1 2 3 檔名開頭請勿使用數字或特殊符號並不要使用中文為檔名

8. 8 Select Device Family, Package, Device and Speed Grade 1 2

9. 9 Finish

10. 10 Create a New File 1.Right Click 2

11. 11 Create a New Module 1 2. Type “ logic ”

12. 12 Define I/O Port 1.Type x,y,z,f 2.Select I/O

13. 13 Finish

14. 14 Type 1.Type 2.Remember to save the file

15. Check Synthesize 2.Double Click 1.Double Click

16. 16 Add Verilog Test Fixture 1.Right Click 2 3 4 5 檔名開頭請勿使用數字或特殊符號 並不要使用中文為檔名

17. 17 Finish 1 2

18. Test bench 18 1 2.Remember to save the file

19. Generate Expected Simulation Result 19 1 2. Double Click

20. 20 Click Zoom Full 1.Run all2.Click

21. 21 Result f=x^y ^z

22. Enter the PlanAhead 22 1 2.Double Click

23. 23 Pins Assign User I/O FPGA Pin Signal LED1  E13  f Sw1  D14  x Sw2  E12  y Sw3  F12  z

24. 24 Assign pins [1] 1 2 3.key in 4

25. 25 Assign pins [2] 3 1 2. key in

26. 26 Assign pins [3] 3 1 2. key in

27. 27 Assign pins [4] 3 1 2. key in 4. Save

28. It’s Generate by PlanAhead 28 1.Double Click 2.

29. 29 Run “ Implement Design ” 1 2. Double Click

30. 30 Select FPGA Start-Up Clock to JTAG Clock 1. Right Click 2 4 3 5

31. 31 Generate Bitstream File Double Click

32. 32 Run “ Configure Device ” Double Click 此時請務必將版子接上

33. Create a New Project on ISE iMPACT 33 1 2

34. 34 Select Boundary.. and Automatically … 2 1

35. 35 Select “ logic.bit file ” 1.Double click 2

36. Press “ok” 36

37. 37 Right-click to select operation 2 1.Right Click

38. 38 Program Succeeded Check the Result on spartan-6

39. 39 Check the Result on spartan-6 DIP SWITCH LED

40. 40 Question and Answer 歷史人物中，誰跑最快 ?