1. Remote Firmware Down Load

2. Xilinx V4LX25 Altera Stratix Control Altera Stratix Control Xilinx V4FX20 EPROM XCF08 EPROM XCF08 EPROM EPC16 EPROM EPC16 EPROM XCF08 EPROM XCF08 EPROM XCF08 EPROM XCF08 Altera Atmel uController EPROM EPC16 EPROM Xilinx Virtex 5 Xilinx Virtex 5 EPROM Xilinx Virtex 5 Xilinx Virtex 5 EPROM Xilinx Virtex 5 Xilinx Virtex 5 EPROM Altera CTPSD TIFADC250 ROC SRAM VXS IsquareC VME Ethernet Firmware Files Firmware Download Diagram for Front-End Readout Modules VXS IsquareC

3. FADC-250 Configuration Scheme JTAG Links Loading Configurarion During Code Development 1)Connect (Altera or Xilinx) JTAG cable 2)Set Dip Switch to select JTAG Chain 3)Run Altera Quartus or Xilinx Impact program to config Devices. Remote Config Loading Configurarion After Installation 1)Control FPGA receives config. data via VME-64 bus and temporary stores to SRAM. Config. data for one or more FPGA can be received at once. 2)Control FPGA programs config. data into EPROM. 3)Control FPGA read back config data from EPROM to SRAM. 4)VME host (ROC) read and compare data. If OK, issue config command. 5)Control FPGA issues config command to EPROM to load new config. data to FPGA.. Altera Stratix (control) Altera CPLD Xilinx LX25 Xilinx LX25 Xilinx FX20 Xilinx FX20 Xilinx LX25 Xilinx LX25 Xilinx XCF08 EPROM Xilinx XCF08 EPROM Xilinx XCF08 EPROM Xilinx XCF08 EPROM Xilinx XCF08 EPROM Xilinx XCF08 EPROM Altera EPC16 EPROM Altera EPC16 EPROM PC SRAM VME USB JTAG FPGA Boot

4. FADC : Config data size: LX25 =.97744 Mbytes FX20 =.90528 Mbytes Stratix = 1.205 Mbyte VME transfer time (VME 30MByte/Sec): LX25 =.032 sec FX20 =.032 sec Stratix =.042 sec VME transfer for 1 FADC (all FPGA) to Control:.14 sec JTAG transfer time (JTAG clock of 3MHz) LX25 = 3 sec FX20 = 3 sec Stratix = 4 sec Time to erase FLASH: LX25, FX20 = 9 sec Stratix = 20.5 sec Time to program FLASH LX25 = 31.3 sec FX20 = 25.0 sec Straitx = 76.5 sec Total ~= 238 sec. ~= 4 minutes. FADC-250 Configuration Time

5. CTP Configuration Scheme JTAG Links Xilinx LX50 Xilinx LX50 Xilinx LX50 Xilinx LX50 Xilinx LX110 Xilinx LX110 Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF32 EPROM Xilinx XCF32 EPROM Remote Config VXS IsquareC Loading Configurarion During Code Development 1)Connect Xilinx JTAG cable 2)Run Xilinx Impact program to config Devices. Loading Configurarion After Installation 1)LX110 config. data via VXS IsquareC and temporary stores to RAM inside FPGA. Config. Data has to be segmented due to limited RAM. 2)LX110 programs config. data into EPROM. 3)LX110 read back config data from EPROM to SRAM. 4)VME host (ROC) read and compare data. If OK, send next segment. 5)VME host (ROC) issues config command when all segments are stored in ROM. 6)LX110 issues config command to EPROM to load new config data to FPGA.. FPGA Boot

6. CTP Configuration Time CTP : Config data size: LX50 = 1.57 Mbytes LX110 = 3.64 Mbytes VME transfers to TI (VME 30MByte/Sec): LX50 =.053 sec LX110 =.122 sec TI transfers to CTP (IsquareC 34.43Kbytes/Sec write; 40.08 Kbytes/Sec read (1) ): LX50 = 56 sec (wr); 40 sec (rd) LX110 = 106 sec (wr); 91 sec (rd) JTAG transfer time (JTAG clock of 3MHz) LX50 = 5.2 sec LX110 = 12 sec Time to erase FLASH: LX50 = 16 sec LX110 = 36 sec Time to program FLASH LX50 = 50 sec LX110 = 117 sec Total ~= 720 sec. ~= 12 minutes. (1) Documentation of I2C Protocol Project, Sebouh Paul

7. VHDL Block Diagram to Remotely Configure FADC-250 VME IFACE CMD REGS EPROM OP-CODE TABLE EPROM OP_CODE SEQUENCER JTAG IFACE VHDL Code to Remotely Configure FPGA AHDL Operating Code Select Altera Control FPGA Altera CPLD SRAM Select JTAG Remote Configurarion Sequence 1)VME host (ROC) write configuration data for one or more FPGA to SRAM (memory map TBD). 2)VME host write CMD Registers to initiate EPROM stored. 3)VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAM. 4)VHDL code relinquishes control of SRAM and signals VME host. 5)VME host verifies EPROM stored data. If OK, write CMD Register to initiate FPGA config. 6)VHDL Code issues config command to EPROM to load new config data to FPGA. VME BUS

8. VHDL Block Diagram to Remotely Configure CTP IsquareC IFACE CMD REGS EPROM OP-CODE TABLE EPROM OP_CODE SEQUENCER JTAG IFACE VHDL Code to Remotely Configure FPGA VHDL Operating Code Select LX110 FPGA JTAG RAM IsquareC Bus Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF16 EPROM Xilinx XCF32 EPROM Xilinx XCF32 EPROM Remote Configurarion Sequence 1)VME host (ROC) write configuration data in segments (Host to TI and then TI to LX110). 2)VME host write CMD Registers to initiate EPROM stored. 3)VHDL Code takes over control of SRAM. Read config. data from SRAM, send OP-Code to EPROM, and stores config data to EPROM. After store, read back EPROM data to SRAM 4)VHDL code relinquishes control of SRAM and signals VME host. 5)VME host verifies EPROM stored data. If OK, repeat for all segmens. 6)When all segments are done, twrite CMD Register to initiate FPGA config. 7)VHDL Code issues config command to EPROM to load new config data to FPGA.