1. Alpha AXP Architecture Dr. Richard L. Sites Dr. Richard L. Sites Digital Technical Journal Digital Technical Journal Volume 4, Number 4 Volume 4, Number 4 Special Issue 1992 Special Issue 1992 Shyam Bukka Friday, January 30, 2004

2. Dr. Richard L. Sites  Employment IBMIBM Hewlett-PackardHewlett-Packard BurroughsBurroughs Digital Equipment Corporation (1980) significant contributor to the Alpha AXP architectureDigital Equipment Corporation (1980) significant contributor to the Alpha AXP architecture  Education B.S. in Mathematics form MITB.S. in Mathematics form MIT Ph.D. in Computer Science from Stanford UniversityPh.D. in Computer Science from Stanford University Post-doctoral work at the University of North Carolina (computer architecture)Post-doctoral work at the University of North Carolina (computer architecture)

3. ALPHA AXP DESIGN GOALS 1. High Performance. 2. Longevity. 3. Capability Of run both VMS and Unix Operating Systems. 4 Easy migration from VAX and MIPS architectures. 1.PAL ( Privileged Architecture Library )code lets Alpha AXP Implementations run the full Open VMS AXP and DEC OSF/1 and Windows NT AXP operating systems. Implementations run the full Open VMS AXP and DEC OSF/1 and Windows NT AXP operating systems.

4. PAL Code It is a Privileged Architecture Library (PAL Code) It is a Privileged Architecture Library (PAL Code) 1. It contains a set of Subroutines that are specific to a particular Alpha AXP Operating System Implementation. particular Alpha AXP Operating System Implementation. PAL Code is written in Standard Machine Code. PAL Code is written in Standard Machine Code. 2. It provides the Operating System Primitives like Context Switching, Interrupts, exceptions and Memory Management. 3. It is written in a standard machine code language and it is accessible by implementation hardware or CALL_PAL instructions.

5. Performance And Longevity Performance : Alpha AXP architecture is listed in Guinness Book Of World Records as the world’s fastest single-chip Microprocessor. Longevity : The longevity of Alpha AXP is increased by 1000 times by the following three considerations. 1. Fast Cycle Time Implementations.(10 times) 2. Multiple Instruction Issue (MII).(10 times) 3. Multiple Processor Implementation.(10 times)

6. Key Design Issues 1.RISC. 2.Full 64-bit design. 3.Register File. 4.Multiple Instruction Issue (MII). 5.Shared Memory Multiprocessing.

7. Multiple Instruction Issue (MII)  MII : Starting more than one instruction at Once. Once. 1.No Branch Delayed Slots. 2.No Suppressed Instructions. 3.No Byte Load/Store Instructions and Implicit Unaligned accesses and no Partial Register Writes. 4.No Arithmetic Exceptions. Cray-1 Model of Arithmetic Exceptions are adopted in first AXP architecture (Exceptions are reported at the end of the event). Cray-1 Model of Arithmetic Exceptions are adopted in first AXP architecture (Exceptions are reported at the end of the event). Explicit TRAPB ( TRAP Barrier) Instruction. Explicit TRAPB ( TRAP Barrier) Instruction.

8. Branch Delayed Slots Address Normal Jump Delayed Jump Optimized Del. Jump 100 101 102 103 104 105 106 LOAD X, A ADD 1, A JUMP 105 ADD A, B SUB C, B STORE A, Z LOAD X, A ADD 1, A JUMP 105 NOP ADD A, B SUB C, B STORE A, Z LOAD X, A JUMP 105 ADD 1, A ADD A, B SUB C, B STORE A, Z

9. Example for Aligned Access 15347814 13441812 11DEFE10 9BCAC8 745EE6 5FE564 345122 1ABFF0 15 8 7 0 16 Bit Data Bus Memory Address Data 1.Accessing Data from 0 th word 2. Data(15:8) = AB 3. Data(7:0) = FF 4. Aligned Access

10. Example for Unaligned Access 15 347814 13 441812 11 DEFE10 9 BCAC8 7 45EE6 5 FE564 3 45122 1 ABFF0 15 8 7 0 Memory Address Data Bus Data 1.Accessing Data from 1 word 2. Data(15:8) = AB 3. Data(7:0) = 12 4.Un aligned Access

11. Shared Memory Multi Processing 1. L oad Locked 2. I n-Register Modify 3. S tore-Conditional 4. T est

12. Data Representation Data Characteristics :  A ll Operations are done between 64-bit Registers.  M M M Memory is accessed via 64-bit Virtual Addresses, using the little-endian or, optionally the big-endian byte numbering convention.  T T T There are 32 integer registers(R31=0) and 32 floating-point registers (F31=0).  L L L Longword(32-bit) and Quadword (64-bit) integers are supported.

13. Data Types 1. Four Integer data types are supported : 1. Four Integer data types are supported : Byte Byte Word Word Longword Longword Quadword Quadword 2. Five floating point data types are supported : 2. Five floating point data types are supported : VAX Floating Point Formats VAX Floating Point Formats  VAX F_floating (32-bit)  VAX G_floating(64-bit) IEEE Floating Point Formats IEEE Floating Point Formats  IEEE single (32-bit)  IEEE double (64-bit)  IEEE extended (128-bit)

14. Integer Data Representation 7 0 : A 1. Byte Format  8-bit Data item.  It is supported by the extract, insert, zap instructions. 2. Word Format 15 0 : A  16-bit Data item.  It is supported by the extract, mask, insert instructions.

15. 3. Longword 31 0  32-bit Data item.  Bit 31 is the Sign bit.  It is supported by sign- extended load/store instructions and longword arithmetic instructions. 4. Quadword : A 63 0  64-bit Data item.  Bit 63 is Sign bit (Signed Integer).  It may be a Signed Integer / Un signed Integer : A

16. VAX Floating Point Formats 1. F_floating Format 1. F_floating Format  Memory Format 31 16 15 14 7 6 0 Frac. HiExp.SFracton. Lo  Register Format 63 62 52 51 29 28 0 SExp.Fraction 0 1. If Exp=0 and S=0 Then Value = 0. 2. If Exp=0 and S=1 Then it is a Reserved Operand. 3. Range 0.29*10**-38 Through 1.7*10**38. 4. Precision is 7 decimal digits.

17. IEEE Floating-Point Formats IEE Floating-Point Formats BasicExtended SingleDouble Single Double The values representable within a format are specified by using three integer parameters.  P --- Number of fraction bits.  Emax --- The Maximum exponent.  Emin --- The Minimum exponent. Within each format following entities are permitted. Numbers of the from (-1)**S x 2**E x b(0).b(1).b(2)……b(P-1) a. S=0 or 1 b. E = any integer between Emin and Emax, inclusive c.b(n) = 0 or 1 d.Two infinities-positive and negative e. At least one Signaling NaN f. At least one Quiet NaN

18. BASIC Basic Floating Data type Formats : 1. Single : A Exp.SFraction. 31 30 23 22 0 S Exp. Fraction 0 63 62 52 51 29 28 0 Memory : A Register 2. Double (T_floatong )  Memory  Register SExponentFraction Hi Fraction Lo 31 30 20 19 0 : A : A+4 SExp.Fraction0 63 62 52 51 32 31 0

19. Instruction Formats 1. Four Fundamental Instruction formats are there in Alpha AXP.  Operate Instructions.  Memory Instructions.  Branch Instructions.  CALL_PAL Instructions. 1.All Instructions are 32-bit wide. 2.They reside aligned long word addresses. 3.Each Instruction contains 6-bit Opcode. And zero to three 5-bit Register-number fields, RA,RB,RC. 4.The remaining bits contains function (opcode extension), Literal, or Displacement fields. RB is never Written and RC is never Read.

20. Operate Instructions Instruction Format : Instruction Format : OPRA Literal 1 0 Func Func. RC Func. RB /// 6 5 5 11 5 Integer, Litteral Integer,Register Floating Point  There are five groups of register-to-register operate instructions : Integer, Arithmetic, logical, byte manipulation and miscellaneous instructions.  All Operate Instructions are three-operand register- to-register instructions and operate on 64-bit Quadwords unless otherwise specified.  The Instruction is in the form of RC=RA Operate RB.  In Integer operates, the opcode and a 7-bit function field specify the exact operation.  Integer operates may have an 8-bit zero-extended literal instead of RB.  In floating-point operates, the opcode and an 11-bit function specify the exact operation.  There are no floating point literals.

21. Example for Opearte Instruction Longword Add : Format : Format : ADDL Ra.rl,Rb.rl,Rc.wq !Operate Format ADDL Ra.rl,Rb.rl,Rc.wq !Operate Format ADDL Ra.rl,#b.rl,Rc.wq !Operate Format ADDL Ra.rl,#b.rl,Rc.wq !Operate Format Operation : Operation : SEXT((Rav+Rbv) )Rc Exceptions : Integer Overflow Instruction Mnemonics : ADDL Add Longword Qualifiers : Integer Overflow Enable (/V)

22. Memory Instruction Instruction Format : OPRARBDisplacement 6 5 5 16 31 26 21 16 0  Memory Format Instructions are used for loads, stores, and a few miscellaneous operations.  Loads /Store are two operand Instructions, Specifying Register RA and a base-displacement virtual byte address.  The effective address calculation sign extends the 16-bit displacement to 64 bits and adds the 64-bit RB register.  The resultant virtual byte address is mappe d to the physical address.  The miscellaneous instructions makes the other uses of RA,RB registers.

23. Example For Memory Instruction Load G_floating : Format : Format : LDG Pa.wg,disp.ab(Rb.ab ) !Memory Format LDG Pa.wg,disp.ab(Rb.ab ) !Memory Format Operation : Operation : Va (Rbv+SEXT(disp)) Va (Rbv+SEXT(disp)) Fa (Va) ||(Va) || Fa (Va) ||(Va) || (Va) ||(Va) (Va) ||(Va) Exception : Exception : Access Violation Access Violation Fault on Read Fault on Read Alignment Alignment Translation Not Valid Translation Not Valid Instruction Mnemonic : Instruction Mnemonic : LDG Load G_floating (Load D-floating) LDG Load G_floating (Load D-floating) Qualifiers : Qualifiers : None. None.

24. Branch Instruction Format Instruction Format : OPRADisplacement 6 5 21 31 26 21 0  Branch Instructions specify a single register RA and a signed PC- Relative longword displacement.  The branch target calculation shifts the 21-bit displacement left by 2 bits to make it long word displacement then sign extends it and adds to the updated PC.  Conditional branch instructions test register RA, and unconditional branches write the updated PC to RA for subroutine linkage.  Calculated jump instructions write the updated PC to RA and then jumps to the target address in RB.

25. Instruction Format : CALL_PAL Instruction OP Function 31 26 0 6 26  The CALL_PAL Instructions has only a 6-bit opcode and a 26-bit function field.  The function field is a small integer specifying one of a few dozen privileged architecture library routines.