1. Computing and the World Walid Taha Rice University

2. The modern computer

3. How it is built C++ Verilog C Assembly FORTRAN VHDL

4. A programming language (PL) Is the face of computing to the world Provides tools for managing complexity Is the right place to fix old, tough bugs

5. My research Create and deploy language features Study existing languages Study important domains Extend existing languages

6. This talk Overview of three research projects General purpose languages (GPLs) Hardware description languages (HDLs) Physically safe computing (PSC)

8. General Purpose Languages

9. Overview Much of our work is on GPLs Real-time and event driven languages Multi-stage programming (MSP) Indexed types

10. Overview Much of our work is on GPLs Real-time and event driven languages Multi-stage programming (MSP) Indexed types more about this today

11. Why MSP? Abstractions manage complexity Abstractions often have runtime cost Programmers avoid runtime cost Abstractions don’t get used...

12. A single stage computation OP I1I1 I2I2 if I 1 = 0 then I 2 *4 else I 2 *8

13. A staged computation OP I1I1 I2I2 O I1I1 P1P1 P2P2 I2I2 if I 1 = 0 then I 2 *4 else I 2 *8 if I 1 = 0 then “ I 2 *4 ” else “ I 2 *8 ”

14. Stage separation OP I1I1 I2I2 O I1I1 P1P1 P2P2 I2I2 if I 1 = 0 then I 2 *4 else I 2 *8 if I 1 = 0 then “ I 2 *4 ” else “ I 2 *8 ” “ I 2 *4 ” “ I 2 *8 ”

15. Strings are not the best way to do this Variable capture (Scheme, CPP, etc) Static type checking (8 years, a huge effort!) Approach Build “f (x,y)” Combine F X Syntactic correctness? Reject “f (x,)” Type correctness? Reject “7 (8)” String  Datatype  The hard part

16. Strings are not the best way to do this Variable capture (Scheme, CPP, etc) Static type checking (8 years, a huge effort!) The hard part Approach Build “f (x,y)” Combine F X Syntactic correctness? Reject “f (x,)” Type correctness? Reject “7 (8)” String  Datatype  MSP 

17. “Killer apps” Anywhere generality is needed, but expensive Interpreters Numerical computation Gaussian elimination Dynamic programming The Fast Fourier Transform (FFT) Web page generation

18. Typical speedup Interpreters: 10-100 times Others: significant variation Real win is often in code quality

20. Hardware Description Languages

21. Hardware (HW) design today Complexity is soaring. Must manage: Gate count (area) Wire delays (speed) Power consumption Temperature effects Mainstream trend: more automation

22. Our approach Say No to Automation! Provide better abstractions Provide better static checking

23. Strengths of this approach Engineers know a lot about design Design and deploy as extension “The Verilog Preprocessor” Working with domain experts Jim Grundy and John O’Leary at Intel Target users are Intel chip designers

24. The Verilog HW description language Developed by HW engineers, based on C Two very different “Verilogs” Structural Behavioral Structural is poor in abstractions & checking

25. Results Verilog is a statically checkable two-level language Bus (array) bound checking Static gate estimation Example: adder (N,x,y) : 2N+7 Tight bound for many circuits Static delay estimation

26. Results Verilog is a statically checkable two-level language Bus (array) bound checking Static gate estimation Example: adder (N,x,y) : 2N+7 Tight bound for many circuits Static delay estimation more about this today

27. Bound checking, Part 1: inconsistencies are padded module invert4(x,y); input [3:0] y; output [3:0] x; assign x = ~ y; endmodule y0y0 y3y3 y2y2 y1y1 x0x0 x3x3 x2x2 x1x1

28. Bound checking, Part 1: inconsistencies are padded module invert4(x,y); input [4:0] y; output [3:0] x; assign x = ~ y; endmodule y0y0 y3y3 y2y2 y1y1 x0x0 x3x3 x2x2 x1x1 y4y4 Valid Verilog Description Padding Semantics

29. Bound checking, Part 2: parameter checks are ad hoc module invertn(x,y); parameter N = 4; input [N-1 : 0] y; output [N-1 : 0] x; genvar i; generate for(i = 0 ; i < N ; i = i + 1) not (x[i],y[i]); endgenerate endmodule y0y0 y3y3 y2y2 y1y1 x0x0 x3x3 x2x2 x1x1

30. Bound checking, Part 2: parameter checks are ad hoc module invertn(x,y); parameter N = 4; input [N-1 : 0] y; output [N-1 : 0] x; genvar i; generate for(i = 0 ; i <= N ; i = i + 1) not (x[i],y[i]); endgenerate endmodule y0y0 y3y3 y2y2 y1y1 x0x0 x3x3 x2x2 x1x1 Off-by-one detected after elaboration NB: Recall buffer overflows...

31. How VPP works Extended Verilog VPP Yices (SMT Solver) Integer Satisfiabilit y Problem I ll- Typed Well- Typed  Integer Satisfiabilit y Problem SMT Problem Yes/No

33. Physically Safe Computing

34. Motivation Computers are permeating our world... Are we safe? Copyright 2007 Hyundai Copyright 2007 New York Times

35. Inspiration “A robot may not injure a human being” - Asimov’s First Law 1942 for i = 1 to 35 read i... 011001... 010010...

36. Goals Accelerate the engineering process Improve virtual testing (Acumen) Guarantee physical safety

37. Goals Accelerate the engineering process Improve virtual testing (Acumen) Guarantee physical safety more about this today

38. Acumen = RIDL + PhyDL RIDL specifies controller The discrete, digital world PhyDL specifies environment The continuous, physical world

39. Small example F  F F

41. Semantics RIDL is translated into event handlers PhyDL is translated into simulation codes Identify state variables Reduce order (to one) Vectorize Simulate (currently, numerically)

42. More telling examples Goal: Active bus suspension U is the control force How do we design controller?

43. More telling examples

45. Closing Words

46. Computing Computing has huge impact on our lives Better computing requires better languages Significantly better languages are possible

47. The World Just describing the real world is hard Tinkering  Fun  Better products The most useful computer is invisible

48. Computing is too important to leave to old, broken languages Thank you

50. Credits

51. Multi-stage Programming Tim Sheard Zino Benaissa Emir Pasalic Amr Sabry Steven Ganz Xavier Leroy Eugenio Moggi Stephan Ellner Michael Florentin Patricia Johann Roumen Kaiabachev Hongwei Xi Cristiano Calcagno Ed Pizzi Kedar Swadi

52. Hardware Description Languages Cherif Salama Yilong Yao Jim Grundy John O’Leary Jennifer Gillenwater Gregory Malecha

53. Physically Safe Computing Walid Taha Marcie O’Malley Corky Cartwright Albert Cheng Paul Hudak Angela Zhu Jun Inoue Alex Stoll Joshua Langsfeld Katherin Davis Kevin Hirshberg Laura Shepard

55. Ongoing and future work MSP and indexed types in Java (“Mint”) Deploying VPP Physically Safe Computing