1. Phase-1 Padring

2. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 2 03/04/2008 Padring Overview 19 500 µm Several Blocs :  JTAG pads  Digital Control pads  Analog Control Pads  Digital Output pads (Low and High speed)  Clocks  PLL for test Every bloc have its own power supply pads. JTAG Digital output Analog Control Digital output Clocks Digital output Analog Control Digital Control Digital output PLL for test

3. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 3 03/04/2008 Design Constrains The padring is more or less symmetrical :  To have a uniform distribution of power supply  To avoid timing problems for the fast readout To facilitate probe testing, most of the Digital pads and the power pads are doubled.  26 Probe pads for I/O pads.

4. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 4 03/04/2008 Digital Output pads  16 Low Speed Digital Output data  4 High Speed Digital Output data : LVDS pads doubled for probing 4 blocks of Digital output have been placed all along the padring. Every bloc contains 1 High Speed and 4 Low Speed Output

5. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 5 03/04/2008 Clocks Clocks pads  CKCMOS: master clock (doubled)  CKR: LVDS readout clock (doubled)  PLL Clock (can be disconnected from the chip if needed) The choice of the clock is done by a mux To avoid timing problem, the following pads have been placed near the Clocks Pads  CLKD : LVDS digital data transmitting clock (doubled)  MK_CLKD : LVDS digital marker and clock (doubled)

6. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 6 03/04/2008 PLL for test 2 versions of a PLL are implemented :  1 PLL for test with probing pads.  1 PLL to generate the master clock with reduced number of pads. When their own power supply pads are disconnected, these PLL are independent from Phase1 Core

7. i PHC Phase 1 Padring Grégory.Bertolone@IReS.in2p3.fr 7 03/04/2008 Questions Thanks for your attention We shall answer to your questions