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A New High Speed, Low Power Adder; Using Hybrid Analog-Digital Circuit Taherinejad, N.; Abrishamifar, A.; Circuit Theory and Design, 2009. ECCTD 2009. European Conference on Digital Object Identifier: 10.1109/ECCTD.2009.5275072 Publication Year: 2009, Page(s): 623 - 626 Adviser : 易昶霈 Student : 杜彥諴
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Outline 1.Introduction 2.Proposed Hybrid Analog-Digital Circuit 3.Simulation 4.Discussion 5.Conclusion
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Introduction (CellPhone, NB, MP3)Mobile system's process Hybrid analog-digital circuit design Analysis general structure of a full adder and delay propagation Critical path delay
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Introduction Analysis General Structure of a Full Adder and Delay Propagation 假設一個邏輯閘的延遲時間為 t , FA 最大的延遲 時間為 carry out(3t)
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Introduction Critical Path Delay 以 ADDER 來說不管是常見 RCA 還是 CLA 在 carry 通常以 delay 最大的
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Proposed Hybrid Analog-Digital Circuit Carry Propagation Summation Three regions
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Proposed Hybrid Analog-Digital Circuit Carry Propagation A new circuit for carry propagation Table-1
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Proposed Hybrid Analog-Digital Circuit Carry Propagation A new circuit for carry propagation 無論是一個 FA 或是 n 個 bit adder , carry 都是最慢 的一個因素 這裡本文提出了一個用混合設計的概念電路 將原本的 3t 電路改成 2t 電路
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Proposed Hybrid Analog-Digital Circuit Carry Propagation A new circuit for carry propagation
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Proposed Hybrid Analog-Digital Circuit Carry Propagation A new circuit for carry propagation
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Proposed Hybrid Analog-Digital Circuit Carry Propagation Table-1
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Proposed Hybrid Analog-Digital Circuit Summation
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Proposed Hybrid Analog-Digital Circuit Summation final circuit
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Proposed Hybrid Analog-Digital Circuit Three regions Logical low(0~0.6 V) Meaningless(0.6~1.2 V) Logical high(1.2~1.8 V)
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Simulation Table-2 Minimum mos specification
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Simulation Table-3 Other special mos specification
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Discussion delay
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Discussion power
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Discussion Table-4
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Conclusion 在不計算 Paper 中 Cout 錯誤的狀況下,此電 路只使用 6(Sout)+10(Cout) 。與文中所示 之一般 Adder(24) 相比,減少了 3 成的 mos 數量 減少了 Carry 的延遲時間,速度由 3t 改善至 2t ,減少了 3 成的時間
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