1. 87 GHz Static Frequency Divider in an InP-based Mesa DHBT Technology S. Krishnan, Z. Griffith, M. Urteaga, Y. Wei, D. Scott, M. Dahlstrom, N. Parthasarathy and M. Rodwell Department of Electrical and Computer Engineering, University of California, Santa Barbara griffith@ece.ucsb.edu 805-893-8044 GaAsIC, October 2002—Monterey, CA

2. Why Static Frequency Dividers (SFD )? MS flip-flops are very widely-used high speed digital circuits: Master-Slave Flip-Flop with inverting feedback Connection as 2:1 frequency divider provides simple test method Standard benchmark of logic speed: Performance comparisons across technologies Dynamic, super-dynamic, frequency dividers: Higher maximum frequency than true static dividers Narrow-band operation  more limited applications High Speed technology performance: HRL: > 100 GHz divider—this conference with E 2 CL UCSB: 75 GHz static dividers using InAlAs/InGaAs TS-HBTs HRL: 72.8 GHz static dividers using InAlAs/InGaAs HBTs

3. f  does not predict logic speed f max does not predict logic speed Large signal operation involves switching time constants  Why Static Dividers, and what makes them fast MS latch: key digital element : resynchronizes data to clock often sets system maximum clock

4. Mesa DHBT Epitaxial Layer Structure InP Emitter n + doped P + InGaAs Base: 52 meV Band gap grading 2000 Å n - InP Collector MaterialDoping (cm -3 )Thickness (  ) n-InGaAs1∙10 19 300 n-InGaAlAs1∙10 19 90 n-InP1∙10 19 900 n-InP8∙10 17 300 n-InGaAlAs8∙10 17 233 p-InGaAlAs2∙10 18 66 p-InGaAs4∙10 19 (Be)400 n-InGaAs2.25∙10 16 100 n-InGaAlAs2.25∙10 16 240 n-InP5.66∙10 18 30 n-InP2.25∙10 16 1630 n-InGaAs1∙10 19 250 n-InP1∙10 19 1250 InPSIN/A

5. mesaIC Process: Key Features  Slide 1

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15. mesaIC Process: overview  Both junctions defined by selective wet-etch chemistry Narrow base mesa allows for low A C to A E ratio Low base contact resistance— Pd based ohmics with  C < 10 -7  ∙cm 2 Collector contact metal and metal ‘1’ used as interconnect metal NiCr thin film resistors = 40  /  MIM capacitor, with SiN dielectric… -- used only for bypass capacitors Low loss, low  r = 2.7 microstrip wiring environment Microstrip wiring environment…. has predictable characteristic impedance controlled-impedance interconnects within dense mixed signal IC’s ground plane eliminates signal coupling that occurs through on-wafer gnd-return inductance

16. DC and RF measurements Common emitter characteristics Device geometry: emitter metal = 0.7  8.0  m 2, real device = 0.6 ∙ 7.0  m 2 Collector to emitter area ratio, A C / A E = 4.5 f  = 205 GHz, f max = 210 GHz Measurement condition: V CE = 1.2 Volts, J c = 2.5 mA/  m 2 I B = 50  A per step DC beta  = 20 Self heating present—not observed in previous runs with same material

17. Circuit diagram: Static Frequency Divider Circuit Details…. ECL topology J EF = 2.0 mA /  m 2 J steering = 2.5 mA /  m 2 V EE = - 4.5 Volts Microstrip interconnects Output voltage for acquire and hold components,  V = 300mV Output buffer used for measurement isolation, V out  300 mV Hold ckt Acquire ckt

18. Chip Photograph: 87 GHz Divider Synthesizer clk Divider Output DC bias DC clk Device Count = 32 Die Area = 0.7 x 0.7 mm 2

19. Measurements: DC – 40 GHz setup Clock input  0 d  m Divider Operation from 4 GHz to 40 GHz Measurement establishes fully static nature of divider Output waveform @ 2 GHz; f clk = 4 GHz V EE DC clk Out Sampling oscilloscope DC - 40 GHz Synthesizer Clk  0 d  m

20. Measurements: 50 – 75 GHz setup Output waveform @ 37.5 GHz; f clk = 75 GHz Clock input  0 d  m Divider Operation from 50 GHz to 75 GHz V EE DC clk Out Sampling oscilloscope DC - 40 GHz Synthesizer Clk  0 d  m Frequency tripler 16.67 – 25 GHz 50 – 75 GHz

21. Measurements: 75 – 110 GHz setup Clock input  9.7 d  m Divider Operation from 75 GHz to 87 GHz Output waveform @ 43.5 GHz; f clk = 87 GHz V EE DC clk Out Sampling oscilloscope Clk  9.7 d  m 20 – 40 GHz Amp Frequency tripler 75 – 110 GHz Amp DC - 40 GHz Synthesizer

22. Conclusions Accomplishments: Demonstrated a fully static, static frequency divider in a narrow triple-mesa DHBT process—up to 87 GHz Future Direction: Reduce device parasitics (r ex, r bb ) and wiring capacitance Increased current density (J E ) reduces Continued lateral scaling of base contact to decrease A E / A C ratio – lower C CB Acknowledgements: This work was support by the Office of Naval Research (ONR--N00014-01-1-0024) and by Walsin Lihwa / UC Core