1. CSE477 L01 Introduction.1Irwin&Vijay, PSU, 2002 ECE484 VLSI Digital Circuits Fall 2014 Lecture 01: Introduction Adapted from slides provided by Mary Jane Irwin. [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

2. CSE477 L01 Introduction.2Irwin&Vijay, PSU, 2002 Course Contents  Introduction to digital integrated circuits l CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design.  Course goals l Ability to design and implement CMOS digital circuits and optimize them with respect to different constraints: size (cost), speed, power dissipation, and reliability  Course prerequisites l ECE 326. Electronic Circuit Design l ECE 282. Logic Design of Digital Systems

3. CSE477 L01 Introduction.3Irwin&Vijay, PSU, 2002 Course Administration  Instructor:George L. Engel gengel@siue.edu www.siue.edu/~gengel  TA:Geetha Ravi gravi@siue.edu  Labs: Need account on ECE machine (see Steve Muren, smuren@siue.edu)  Text: Digital Integrated Circuits, 2 nd Edition Rabaey et. al., ©2002

4. CSE477 L01 Introduction.4Irwin&Vijay, PSU, 2002 Background from ECE282 and ECE326  Basic circuit theory l resistance, capacitance, inductance l MOS gate characteristics  Hardware description language l VHDL or verilog  Logic design l logical minimization, FSMs, component design

5. CSE477 L01 Introduction.5Irwin&Vijay, PSU, 2002 Transistor Revolution  Transistor –Bardeen (Bell Labs) in 1947  Bipolar transistor – Schockley in 1949  First bipolar digital logic gate – Harris in 1956  First monolithic IC – Jack Kilby in 1959  First commercial IC logic gates – Fairchild 1960  TTL – 1962 into the 1990’s  ECL – 1974 into the 1980’s

6. CSE477 L01 Introduction.6Irwin&Vijay, PSU, 2002 MOSFET Technology  MOSFET transistor - Lilienfeld (Canada) in 1925 and Heil (England) in 1935  CMOS – 1960’s, but plagued with manufacturing problems  PMOS in 1960’s (calculators)  NMOS in 1970’s (4004, 8080) – for speed  CMOS in 1980’s – preferred MOSFET technology because of power benefits  BiCMOS, Gallium-Arsenide, Silicon-Germanium  SOI, Copper, …

7. CSE477 L01 Introduction.7Irwin&Vijay, PSU, 2002 Moore’s Law  In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time).  Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s. l 2300 transistors, 1 MHz clock (Intel 4004) - 1971 l 16 Million transistors (Ultra Sparc III) l 42 Million, 2 GHz clock (Intel P4) - 2001 l 140 Million transistor (HP PA-8500)

8. CSE477 L01 Introduction.8Irwin&Vijay, PSU, 2002 Intel 4004 Microprocessor

9. CSE477 L01 Introduction.9Irwin&Vijay, PSU, 2002 Intel Pentium (IV) Microprocessor

10. CSE477 L01 Introduction.10Irwin&Vijay, PSU, 2002 State-of-the Art: Lead Microprocessors

11. CSE477 L01 Introduction.11Irwin&Vijay, PSU, 2002 Moore’s Law in Microprocessors 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 0.001 0.01 0.1 1 10 100 1000 19701980199020002010 Year Transistors (MT) 2X growth in 1.96 years! Transistors on lead microprocessors double every 2 years Courtesy, Intel

12. CSE477 L01 Introduction.12Irwin&Vijay, PSU, 2002 Evolution in DRAM Chip Capacity 1.6-2.4  m 1.0-1.2  m 0.7-0.8  m 0.5-0.6  m 0.35-0.4  m 0.18-0.25  m 0.13  m 0.1  m 0.07  m human memory human DNA encyclopedia 2 hrs CD audio 30 sec HDTV book page 4X growth every 3 years!

13. CSE477 L01 Introduction.13Irwin&Vijay, PSU, 2002 Die Size Growth 4004 8008 8080 8085 8086 286 386 486 Pentium ® proc P6 1 10 100 19701980199020002010 Year Die size (mm) ~7% growth per year ~2X growth in 10 years Die size grows by 14% to satisfy Moore’s Law Courtesy, Intel

14. CSE477 L01 Introduction.14Irwin&Vijay, PSU, 2002 Clock Frequency Lead microprocessors frequency doubles every 2 years P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 1000 10000 19701980199020002010 Year Frequency (Mhz) 2X every 2 years Courtesy, Intel

15. CSE477 L01 Introduction.15Irwin&Vijay, PSU, 2002 Power Dissipation P6 Pentium ® proc 486 386 286 8086 8085 8080 8008 4004 0.1 1 10 100 197119741978198519922000 Year Power (Watts) Lead Microprocessors power continues to increase Courtesy, Intel Power delivery and dissipation will be prohibitive

16. CSE477 L01 Introduction.16Irwin&Vijay, PSU, 2002 Power Density 4004 8008 8080 8085 8086 286 386 486 Pentium® proc P6 1 10 100 1000 10000 19701980199020002010 Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Power density too high to keep junctions at low temp Courtesy, Intel

17. CSE477 L01 Introduction.17Irwin&Vijay, PSU, 2002 Design Productivity Trends 2003 19811983 19851987 1989 199119931995199719992001 2005 2007 2009 Logic Tr./Chip Tr./Staff Month. x x x x x x x 21%/Yr. compound Productivity growth rate x 58%/Yr. compounded Complexity growth rate 10,000 1,000 100 10 1 0.1 0.01 0.001 Logic Transistor per Chip (M) 0.01 0.1 1 10 100 1,000 10,000 100,000 Productivity (K) Trans./Staff - Mo. Complexity Courtesy, ITRS Roadmap Complexity outpaces design productivity

18. CSE477 L01 Introduction.18Irwin&Vijay, PSU, 2002 Technology Directions: SIA Roadmap Year199920022005200820112014 Feature size (nm)180130100705035 Mtrans/cm 2 714-2647115284701 Chip size (mm 2 )170170-214235269308354 Signal pins/chip7681024 128014081472 Clock rate (MHz)6008001100140018002200 Wiring levels6-77-88-999-1010 Power supply (V)1.81.51.20.90.6 High-perf power (W)90130160170174183 Battery power (W)1.42.02.42.02.22.4 For Cost-Performance MPU (L1 on-chip SRAM cache; 32KB/1999 doubling every two years) http://www.itrs.net/ntrs/publntrs.nsf

19. CSE477 L01 Introduction.19Irwin&Vijay, PSU, 2002 Why Scaling?  Technology shrinks by ~0.7 per generation  With every generation can integrate 2x more functions on a chip; chip cost does not increase significantly  Cost of a function decreases by 2x  But … l How to design chips with more and more functions? l Design engineering population does not double every two years…  Hence, a need for more efficient design methods l Exploit different levels of abstraction

20. CSE477 L01 Introduction.20Irwin&Vijay, PSU, 2002 Design Abstraction Levels SYSTEM GATE CIRCUIT V out V in CIRCUIT V out V in MODULE + DEVICE n+ SD G

21. CSE477 L01 Introduction.21Irwin&Vijay, PSU, 2002 Major Design Challenges  Microscopic issues l ultra-high speeds l power dissipation and supply rail drop l growing importance of interconnect l noise, crosstalk l reliability, manufacturability l clock distribution  Macroscopic issues l time-to-market l design complexity (millions of gates) l high levels of abstractions l reuse and IP, portability l systems on a chip (SoC) l tool interoperability YearTech.ComplexityFrequency3 Yr. Design Staff Size Staff Costs 19970.3513 M Tr.400 MHz210$90 M 19980.2520 M Tr.500 MHz270$120 M 19990.1832 M Tr.600 MHz360$160 M 20020.13130 M Tr.800 MHz800$360 M