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Published bySolomon Caldwell Modified over 9 years ago
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High Speed, Low Power FIR Digital Filter Implementation Presented by, Praveen Dongara and Rahul Bhasin
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Flow Chart Motivation Brief Discussion on FIR Full Adder Design Pipelined Multiplier (8 X 8) Pipelined adder (16 X 16) Results Trouble shooting
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Motivation FIR - Finite Impulse Response Filter –Fundamental processing unit in DSP systems High frequency applications –Video imaging Low power applications –Wireless communications
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Brief Discussion on FIR Filters An N-tap FIR filter can be described by: Direct Implementation T sample T M + T A
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FIR Discussion contd. 2-parallel FIR Filter Parallel Processing Advantage –Reduced power consumption –Or high speed Disadvantage –Overhead of area 2-parallel design
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Why Pipelined/Parallel ? Pipelined to enable higher sampling rates –Sampling frequency can be increased n-fold if we have n pipeline stages. Parallel for low power
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Why Pipelined/Parallel? Contd. - V can be decreased by - C increases by L (L=2) - f can be decreased by L
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Optimizations at various levels Improvement Achieved Levels of design hierarchy
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Full Adder Dynamic Logic True Single Phase Clocking (TSPC)
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Full Adder contd.
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Pipelined Multiplier Baugh-Wooley Algorithm for 8 X 8 multiplication 2’s complement numbers
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Pipelined Multiplier Floor Plan Latency of 12 cycles Partial product summing full adder array Vector merge adder Latch stages to skew the multiplier bits b0-b7 Deskewing latches for the product bits
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Pipelined Multiplier Layout
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Pipelined Multiplier contd. Example –Input vectors 111111a1 X 0101010b If a=1 and b=1 we have the following output sequence. –1111111110101011
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Pipelined Multiplier contd.
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16 X 16 Pipelined Adder Latency of 8 cycles Triangular array of half adders Merging of two half adder rows –Leads to decrease in latency Advantage –Regularity of design –Fewer deskewing latches
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16 X 16 Pipelined Adder Layout
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FIR Filter Layout
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Results
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Trouble Shooting Convergence problems Elmore/Penfield analysis requires lot of disk space and time
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