1. A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology
Shahriar Shahramian
Sorin P. Voinigescu
Anthony Chan Carusone
Department of Electrical & Computer Eng.
University of Toronto
Canada

2. Introduction & Motivation I
Equalization required at high bit rates
Analog equalization up to 40 Gb/s
Digital equalization is more robust and flexible
Digital Equalizer
Photo
Detector
T/H
ADC
Adaptive
Equalizer
Clock
Recovery
Equalized
Data
Require full rate Track & Hold Amplifiers

3. Introduction & Motivation II
Demonstrated 40-GS/sec THA in SiGe BiCMOS
fT and fMAX of 160 GHz
CMOS technologies scaling to nanometre
fT and fMAX exceed 200 GHz for in production CMOS
CMOS is a serious contender for implementing DSP based equalizers above 10 Gb/s

4. Switched Emitter Follower
Introduction & Motivation III
Diode Sampling Bridge
Switched Emitter Follower
J. C. Jensen, et. al.
CICC 02
S. Shahramian, et. al.
CSICS 05
High speed
Low dynamic range
Requires diodes
High speed
Lower supply
Isolation in hold mode

5. Switched Source Follower
Introduction & Motivation IV
Series CMOS Sampler
Switched Source Follower
I. H. Wang, et. al.
Electronic Letters 06
This work
CICC 06
Low supply
Low speed due to series CMOS RON
Take advantage of high speed CMOS source follower

6. 0.13-µm CMOS Technology Simulated fT and fMAX of 80 GHz
8 layer metallization back end with thick RF top metal layers
Available triple-well CMOS transistors
Available low power (high VTH) transistors

7. THA Block Diagram Data Path Output Input T/H Clock Clock Path TIA TIA
DRV CS
TIA
T/H
Diff.
Pair
Diff.
Pair
Input
Output
DRV CS
Clock
TIA
CML
INV
Clock Path CS

8. Input Stage Design
TIA
Active loads
Improve open loop
Gain, T

9. Input Stage Design Eliminating current source transistor reduces power
TIA
Eliminating current
source transistor
reduces power
supply voltage

10. Input Stage Design
TIA
Signal matching
through resistive
feedback

11. Input Stage Design
TIA
Noise matching
through transistor
sizing

12. Input Stage Design Transistors biased at J = 0.25 mA/µm,
TIA
Transistors biased
at J = 0.25 mA/µm,
increased noise
figure for higher
bandwidth
Simulated bandwidth: 30 GHz
Simulated input integrated noise over 30 GHz: 0.5 mVrms

13. Input Stage Design Inductors improve bandwidth, input
TIA
Inductors improve
bandwidth, input
matching and filter
high frequency
noise

14. Input Stage Design
TIA CS
Transistors Q1 and Q2 are diode-connected at DC and
therefore can bias the next CS stage

15. THA Stage Design
T/H
Switched source
follower for maximum
bandwidth

16. THA Stage Design T/H During Track, QSF acts as a source follower
with current IT

17. THA Stage Design T/H During Hold, IT flows through RL which turns
QSF off and isolates CH

18. THA Stage Design T/H QT and QH operate in digital mode and
thus are biased at
J = 0.15mA/µm

19. used to drive QT further
THA Stage Design
T/H
High VTH devices are
used to drive QT further
into “OFF” region and
reduce leakage

20. triple well transistor to
THA Stage Design
T/H
QSF is implemented as a
triple well transistor to
reduce VEFF and lower
power supply voltage

21. THA Stage Design T/H A linear buffer drives the T/H block with 600mVPP
Diff.
Pair
T/H
A linear buffer drives the T/H block with 600mVPP
input and output swing

22. THA Stage Design
Diff.
Pair
T/H
Capacitor Cfth is used to match QSF-CGS and thus cancel
input signal feedthrough during hold mode

23. THA Stage Design
Diff.
Pair
DRV
T/H
A linear output driver provides signal to external
50Ω resistors and measurement equipment

24. Clock Distribution Converts a single-ended 30-GHz clock signal
CML
INV
Converts a single-ended 30-GHz clock signal
to a differential signal with 750mVPP swing

25. Chip Micrograph
Manufactured using IBM’s 0.13µm CMOS technology
The circuit operates from a 1.8V supply and consumes 150mA.
TIA CS
Diff. Pair
Diff. Pair
DRV
THA
CML INV
CML INV
1mm
CML INV
TIA CS
1mm

26. Measurement Results: SP

27. Measurement Results: SP II

28. Time Domain

29. Frequency Domain I

30. Frequency Domain II

31. Frequency Domain III

32. Circuit Comparison fsample [GS/s] Track BW [GHz] THD [dB @ fin] Supply
[V]
Power
[mW]
Process
[N / fT]
This Work 30 7
1GHz
7GHz
1.8
270
CMOS
0.13µm
I. H. Wang el. al.
Electronic Letters 06 10
N/A
5GHz
200
0.18µm
J. Lee et. al.
JSSC 03 12 14
12GHz
-5.2
390
InP
120 GHz
S. Shahramian et al.
CSICS 05 40 43
20GHz
10GHz
3.6
540
SiGe
160 GHz
Y. Lu et. al.
BCTM 05
5.5
1.5GHz
3.5
700
200 GHz

33. Conclusion
CMOS emerges as a contender for high speed DSP based equalizers
Discussed the design methodology for CMOS switched source follower THA
Demonstrated the first 30-GS/sec THA in CMOS

34. Acknowledgement CMC for chip fabrication and providing CAD tools
NSERC for financial support
OIT and CFI for equipment
ECIT for providing the network analyzer