1. International ERD TWG Emerging Research Devices Working Group Face-to-Face Meeting Emerging Research Memory Devices Victor Zhirnov and Rainer Waser Seoul, Korea and San Francisco, CA December 6 and 14, 2008

2. 2 Agenda u R eview decisions from 2008 meetings u Structure changes u Content changes u Review revised memory table draft u Technical Discussion on Specific Emerging Memory Devices

3. 3 2008 Important Events u Emerging Research Memory Devices Workshop v Koenigswinter, Germany, April 2, 2008 u ERD Face-to-Face workshop and meeting v Tsukuba, Japan, September 22-23, 2008 u Fundamental Studies: Physical performance bounds for emerging memories v 2008 focus: Electronic effects RRAM v Team: n V. Zhirnov and R. Cavin / SRC n R. Waser and H. Schroeder /Juelich Research Center

4. 4 2008 Fundamental Studies Physical performance bounds for emerging memories u Our interest in the fundamental limits for emerging memory technologies is driven by the growing importance for embedded memory systems as reflected by the 2007 ITRS u A wide array of different physical phenomena is being proposed as a basis for new high-performance memory devices. v However, remarkably little is known about the ultimate potential of these technologies. u A purpose of the proposed fundamental study is to comprehend the potential performance limits for each of these new memory devices. u Successful execution of the proposed study would be of a considerable value both for ITRS ERD Memory section and for the planning of all research programs on memory.

5. 5 Table 64b: Resistance-based memory technologies (2007 version) Nanomechanical memory Fuse/Anti fuse Memory Ionic Memory Electronic effects Memory Polymer Memory Molecular Memories Storage Mechanism Electrostatically- controlled bi- stable mechanical switch Thermo- chemical redox process Ion transport in solids Multiple mechanisms Not known Cell Elements1T1R or 1D1R Device Types CNT bridge CNT cantilever Si cantilever Nanoparticle M -I-M e.g. Pt/NiO/Pt 1) Solid Electrolyte 2) RedOx reaction 1) Charge trapping 2) Mott transition 3) FE Barrier effects M-I-M (nc)-I-M Bi-stable switch

6. New Memory Candidates u Nanowire Phase-change memory u Magnetic Domain Wall Motion memory v Magnetic race-track memory n Stuart Parkin, “Magnetic race-track – a novel storage class spintronic memory”, Intern J. Mod. Physics B 22 (2008) 117 u Spin transfer torque MRAM DECISION MADE: Not include in 2009 DECISION MADE: Include into ERD memory table

7. Feedback on 2007 ERD Chapter Emerging Research Memory Devices ♦ Transfers  Engineered Tunnel Barrier Memory to PIDS and FEP  Keep the Ferroelectric FET Memory Technology in ERD  Include STT RAM as a new entry. Given progress, should we include STT RAM in a new Potential Solution Table for Memory Technologies? ♦ Other comments  Re-combine the capacitive and resistive memory tables  Discuss other materials (in addition to Pt/NiO/Pt) for Fuse/Anti-fuse Memory  Try to elucidate fundamental limits of Memory Devices  Add a new row to memory table to include Storage Capacity  Address Memory Architecture, perhaps in the Architecture Section  Why do all the memory technology entries have for “Best Projected Write Cycles” a value of 3E16 ?  Include scaling projections for all Memory Technology Entries  The Memory Group is preparing a single reference document containing scaling projections and citations

8. 8 Memory Technologies for the 2009 new ERD Chapter: Summary of decided content changes u Numerical data will be updated v 2008 ERD Memory workshop results v Most recent literature search v Fundamental studies u Add new entry for the Spin- transfer torque MRAM u Add new entry for the Nanowire Phase-change memory u Support Memory Architecture section in ERA

9. 9 Electronic Effects Memory u Charge trapping u Mott transition u Ferroelectric Barrier effects FS result: will not survive scaling to 100 nm and below

10. 2009 Events u SRC/A-STAR Forum on Extremely-Scaled Semiconductor Memory Technologies v Place: Singapore v Time: October 2009 (tentative) u Prospectus u The remarkable progress in semiconductor memory technology has enabled an amazing array of consumer products. However, it is becoming increasingly clear that in information processing applications; especially those utilizing the emerging multi-core processors, rapid access to dense, non-volatile, embedded memory is the key to obtaining maximum performance. The trend to stacked processor/memory structures clearly indicates the need for substantial decreases in memory access times. A fundamental question is the trade-off between non-volatile memory densities and access times. In particular, what can be called “The Voltage-Time Dilemma” appears to characterize the limits of semiconductor memory scaling and performance. At the most basic level, the need for high voltages to obtain rapid access to data impacts both the scaling of devices and the ability of the memory element to operate in a non-volatile mode. This forum will examine the limits of scaling and performance for emerging non- volatile semiconductor memories. 10