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Formal Model for Simulations Instructor: DR. Lê Anh Ngọc Presented by – Group 6: 1. Nguyễn Sơn Hùng 2. Lê Văn Hùng 3. Nguyễn Xuân Hậu 4. Nguyễn Xuân Tùng.

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Presentation on theme: "Formal Model for Simulations Instructor: DR. Lê Anh Ngọc Presented by – Group 6: 1. Nguyễn Sơn Hùng 2. Lê Văn Hùng 3. Nguyễn Xuân Hậu 4. Nguyễn Xuân Tùng."— Presentation transcript:

1 Formal Model for Simulations Instructor: DR. Lê Anh Ngọc Presented by – Group 6: 1. Nguyễn Sơn Hùng 2. Lê Văn Hùng 3. Nguyễn Xuân Hậu 4. Nguyễn Xuân Tùng

2 AGENDA 1. Introduction and Problem Specifications 2. Communication Systems 3. Modeling Process 4. Admissibility 5. Simulations 2/33

3 1. Introduction There are so many way to be solved specifying a problem in DS that we approach about system simulations and algorithms instead of looking inside an algorithm. It is focused on the interface between the device's algorithm or processor with the outside world. 3/33

4 Introduction 4/33

5 Techniques applied Layering is the technique that allows system designers to control the complexity of building large-scale systems Specification sub-system P as a set of inputs in(P), a set of outputs out(P), and a set of allowable sequences seq(P) of inputs and outputs: 5/33

6 Problem Specifications Problem specification when put conditions (sequence, time,...) on processor states as they relate to each other and to initial states. 6/33

7 Problem Specifications inputs: ◦ T 0, …, T n-1  T i indicates p i wants to try to enter the critical section ◦ E 0,…, E n-1  E i indicates p i wants to exit the critical section outputs: ◦ C 0,…,C n-1  C i indicates p i may now enter the critical section ◦ R i,…,R n-1  R i indicates p i may now enter the remainder section Mutual Exclusion Example 7/33

8 Problem Specifications a sequence  of inputs and outputs is allowable iff, for each i, ◦ | i cycles through Ti, Ci, Ei, Ri  each proc cycles through trying, critical, exit, and remainder sections in that order ◦ whenever Ci occurs, most recent preceding input or output for any j ≠ i is not Cj  only one process is in the critical section at a time Mutual Exclusion Example 8/33

9 Problem Specifications Mutual Exclusion Example: allowable Mutual Exclusion T1T1 R1R1 p1p1 p0p0 p2p2 T2T2 C2C2 E2E2 R2R2 T0T0 C0C0 E0E0 T 0 T 1 C 0 T 2 E 0 C 2 R 1 E 2 R 2 … 9/33

10 Problem Specifications Mutual Exclusion Example: not allowable Mutual Exclusion T1T1 p1p1 p0p0 p2p2 T2T2 C2C2 T0T0 C0C0 E0E0 T 0 T 1 C 0 T 2 C 2 … E 0 C 2 … C2C2 10/33

11 2. Communication Systems So Far So far, we have explicitly modeled the communication system ◦ inbuf and outbuf state components and deliver events for message passing, ◦ explicit shared variables as part of configurations for shared memory Not so convenient when we want to study how to provide one kind of communication in software, given another kind. 11/33

12 Different Kinds of Communication Systems Message passing vs. shared memory ◦ different interfaces (sends/receives vs. invocations/responses) Within message passing: ◦ different levels of reliability, ordering ◦ different guarantees on content (when malicious failures are possible) Within shared memory: ◦ different shared variable semantics 12/33

13 What Kinds of Simulations? How to provide broadcast (with different reliability and ordering guarantees) on top of point-to-point message passing How to provide shared objects on top of message passing How to provide one kind of shared objects on top of another kind How to provide stronger synchrony on top of an asynchronous system How to provide better-behaved faulty processors on top of worse-behaved ones 13/33

14 New Way to Model Communication Systems Interpose a communication system between the processors A particular type of communication system is specified using the approach just described ◦ focus on the desired behavior of the communication system, as observed at its interface, instead of the details of how that behavior is provided 14/33

15 Asynchronous Point-to-Point Message Passing Example Interface is: inputs: send i (M) ◦ models p i sending set of msgs M ◦ each msg indicates sender and recipient (must be consistent with assumed topology) outputs: recv i (M) ◦ models p i receiving set of msgs M ◦ each msg in M must have p i as its recipient 15/33

16 Asynch MP Example (cont…) For a sequence of inputs and outputs (sends and receives) to be allowable, there must exist a mapping  from the msgs in recv events to msgs in send events s.t. ◦ each msg in a recv event is mapped to a msg in a preceding send event ◦ is well-defined: every msg received was previously sent (no corruption or spurious msgs) ◦ is one-to-one: no duplicates ◦ is onto: every msg sent is received 16/33

17 Asynchronous Broadcast Example Inputs: bc-send i (m) ◦ an input to the broadcast service ◦ p i wants to use the broadcast service to send m to all the procs Outputs: bc-recv i (m,j) ◦ an output of the broadcast service ◦ broadcast service is delivering msg m, sent by p j, to p i 17/33

18 Asynch Bcast Example (cont…) A sequence of inputs and outputs (bc-sends and bc-recvs) is allowable iff there exists a mapping  from each bc-recv i (m,j) event to an earlier bc-send j (m) event s.t. ◦ is well-defined: every msg bc-recv'ed was previously bc-sent ◦ restricted to bc-recv i events, for each i, is one-to- one: no msg is bc-recv'ed more than once at any single proc. ◦ restricted to bc-recv i events, for each i, is onto: every msg bc-sent is received at every proc. 18/33

19 3. Modeling Process May be several algorithms (processes) runs on each processor to simulate the desired communication system. For example, a processor run two algorithms (processes) at the same time ◦ one process (algorithm) that uses the broadcast service ◦ another process (algorithm) that implements the asynchronous broadcast system on top of the asynchronous point-to-point message-passing system Proposed facility 19/33

20 Modeling Process (Cont.) Ordering of process, forming a “Stack of protocols” ◦ Environment communicates with the top layer ◦ Each process uses communication primitives to interact with the layer beneath it ◦ The bottom layer communicates with the Communication System Algorithm (process) composition 20/33

21 Simulation for Modeling Process layer 1layer 2layer 3 environment communication system modeled as a problem spec (interface & allowable sequences) modeled as a problem spec (interface & allowable sequences) modeled as state machines communicate via appropriate primitives: shared events Layered model 21/33

22 Simulation for Modeling Process (Cont…) layer 1layer 2layer 3 environment communication system Send Propagation of events 22/33

23 Modeling Process Specifications (Cont…) A system consists of ◦ A collection of n processors (or nodes), p 0 through p n-1 ◦ A communication system C linking the nodes ◦ Environment E Notes ◦ Environment E and Communication system C are given as problem specifications ◦ Node is a hardware notion ◦ Running on each node are one or more processes  Processes are organized into a single stack of layers  The same number of layers on each node 23/33

24 Modeling Process Specifications (Cont…) Each process is state machine (modeled as an automaton) ◦ Has a set of states, including a subset of initial states ◦ Has hour kinds of events  Inputs coming in from the layer above (or the environment, if this is the top layer)  Outputs going out to the layer above  Inputs coming in from the layer below (or the communication system, if this is the bottom layer)  Outputs going out to the layer below ◦ Events of type 1 and 2 form the top interface of the process ◦ Events of type 3 and 4 form the bottom interface of the process 24/33

25 layer i - 1 layer i layer i + 1 Propagation of events Top interface of layer i Bottom interface of layer i 12 34 25/33

26 Modeling Process Specifications (Cont…) Events ◦ Concepts  An event is said to be enabled in a state of a process if there is a transition from that state labeled with that event  Inputs from the environment and from the communication system are called node inputs A configuration of the system specifies a state for every process on every node ◦ A configuration does not include the state of the communication system ◦ An initial configuration contains all initial states 26/33

27 Modeling Process Specifications (Cont…) An execution of the system is a sequence C 0 e 1 C 1 e 2 C 2 … of alternating configurations C i and events e i ◦ If it is finite, ending with a configuration ◦ Satisfies the following conditions  C 0 is an initial configuration  event e i is enabled in C i-1 (there is a transition from the state(s) of the relevant process(es) in C i-1 labeled e i )  state components of processes change according to the transition functions for e i  can chop the execution into pieces so that  each piece starts with a node input  all events in each piece occur at the same node  the next node input does not occur until no events (other than node inputs) are enabled Schedule of an execution is the sequence of events in execution, without the configurations. ◦ top()/bot() are schedule only including the events of the top/bottom 27/33

28 4. Admissibility We only require an algorithm to be correct if ◦ each process is given enough opportunities to take steps (called fairness) ◦ the communication system behaves "properly" and ◦ the environment behaves "properly" Executions satisfying these conditions are admissible. 28/33 Definition of Admissible Execution

29 Proper Behavior of Communication System The restriction of the execution to the events of the interface at the "bottom of the stack" is an allowable sequence for the problem specification corresponding to the underlying communication system Example: message passing, every message sent is eventually received 29/33

30 Proper Behavior of Environment The environment (user) interacts "properly" with the top layer of the stack (through the interface events) as long as the top layer is also behaving properly. Mutex example: the user only requests to leave the critical section if it is currently in the critical section. 30/33

31 5. Simulations System C 1 simulates system C 2 if there is a set of processes, one per node, called Sim s.t. 1. top interface of Sim is the interface of C 2 2. bottom interface of Sim is the interface of C 1 3. For every admissible execution  of Sim, the restriction of  to the interface of C 2 is allowable for C 2 (according to its problem spec). 31/33

32 Simulations Sim Sim 0 C 2 inputs C 2 outputs C 1 inputs C 1 outputs C1C1 Sim n-1 C 2 inputs C 2 outputs C 1 inputs C 1 outputs … C2C2 If user of C 2 behaves properly and if C 1 behaves properly, then Sim ensures that user of C 2 thinks it is really using C 2 (and not C 1 plus a simulation layer) 32/33

33 Thank you for listening 33/33


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