1. Chapter 4 Wafer Manufacturing and Epitaxy Growing
Hong Xiao, Ph. D.
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2. Objectives Give two reasons why silicon dominate
List at least two wafer orientations
List the basic steps from sand to wafer
Describe the CZ and FZ methods
Explain the purpose of epitaxial silicon
Describe the epi-silicon deposition process.
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3. Crystal Structures Amorphous Polycrystalline Single crystal
No repeated structure at all
Polycrystalline
Some repeated structures
Single crystal
One repeated structure
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4. Amorphous Structure Hong Xiao, Ph. D.
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5. Polycrystalline Structure
Grain Boundary
Grain
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6. Single Crystal Structure
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7. Why Silicon? Abundant, cheap
Silicon dioxide is very stable, strong dielectric, and it is easy to grow in thermal process.
Large band gap, wide operation temperature range.
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8. Source: http://www.shef.ac.uk/chemistry/web-elements/nofr-key/Si.html
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Source:

9. Unit Cell of Single Crystal Silicon
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10. Crystal Orientations: <100>z
<100> plane y x
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11. Crystal Orientations: <111>z
<111> plane
<100> plane y x
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12. Crystal Orientations: <110>z
<110> plane y x
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13. <100> Orientation Plane
Basic lattice cell
Atom
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14. <111> Orientation Plane
Basic lattice cell
Silicon atom
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15. <100> Wafer Etch Pits
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16. <111> Wafer Etch Pits
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17. Illustration of the Defects
Impurity on substitutional site
Silicon Atom
Impurity in Interstitial Site
Silicon Interstitial
Vacancy or Schottky Defect
Frenkel Defect
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18. Dislocation Defects Hong Xiao, Ph. D.
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19. From Sand to Wafer Quartz sand: silicon dioxide
Sand to metallic grade silicon (MGS)
React MGS powder with HCl to form TCS
Purify TCS by vaporization and condensation
React TCS to H2 to form polysilicon (EGS)
Melt EGS and pull single crystal ingot
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20. From Sand to Wafer (cont.)
Cut end, polish side, and make notch or flat
Saw ingot into wafers
Edge rounding, lap, wet etch, and CMP
Laser scribe
Epitaxy deposition
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21. From Sand to Silicon SiO2 Heat (2000 ° C) + C ® Si + CO2
Sand Carbon MGS Carbon Dioxide
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22. Silicon Purification I
Hydrochloride
Reactor, 300 C
Si + HCl
 TCS
Silicon Powder
Condenser
Filters
Pure TCS with %
Purifier
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23. Polysilicon Deposition, EGS
Heat (1100 C)
SiHCl 3 H 2
Si HCl
TCS Hydrogen EGS Hydrochloride
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24. Silicon Purification II
Process Chamber
EGS H2
H2 and TCS
Liquid TCS
TCS+H2EGS+HCl
Carrier gas bubbles
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25. Electronic Grade Silicon
Source:
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26. Crystal Pulling: CZ method
Single Crystal Silicon Seed
Quartz Crucible
Single Crystal silicon Ingot
Molten Silicon
Heating Coils
1415 °C
Graphite Crucible
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27. CZ Crystal Pullers Mitsubish Materials Silicon
Source:
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28. Source: http://www.fullman.com/semiconductors/_crystalgrowing.html
CZ Crystal Pulling
Source:
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29. Floating Zone Method Poly Si Rod Molten Silicon Heating Coils Movement
Single Crystal Silicon
Seed Crystal
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30. Comparison of the Two Methods
CZ method is more popular
Cheaper
Larger wafer size (300 mm in production)
Reusable materials
Floating Zone
Pure silicon crystal (no crucible)
More expensive, smaller wafer size (150 mm)
Mainly for power devices.
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31. Ingot Polishing, Flat, or Notch
Flat, 150 mm and smaller
Notch, 200 mm and larger
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32. Wafer Sawing Coolant Orientation Notch Crystal Ingot Saw Blade
Ingot Movement
Diamond Coating
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33. Parameters of Silicon Wafer
Wafer Size
(mm)
Thickness (m m)
Area
(cm 2 )
Weight
(grams)
279
20.26
1.32
381
45.61
4.05
100
525
78.65
9.67
125
625
112.72
17.87
150
675
176.72
27.82
200
725
314.16
52,98
300
775
706.21
127.62
50.8 (2 in)
76.2 (3in)
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34. Wafer Edge Rounding Wafer movement Wafer Wafer Before Edge Rounding
Wafer After Edge Rounding
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35. Wafer Lapping Rough polished conventional, abrasive, slurry-lapping
To remove majority of surface damage
To create a flat surface
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36. 3 Si + 4 HNO3 + 6 HF  3 H2SiF6 + 4 NO + 8 H2O
Wet Etch
Remove defects from wafer surface
4:1:3 mixture of HNO3 (79 wt% in H2O), HF (49 wt% in H2O), and pure CH3COOH.
Chemical reaction:
3 Si + 4 HNO3 + 6 HF  3 H2SiF6 + 4 NO + 8 H2O
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37. Chemical Mechanical Polishing
Pressure
Slurry
Wafer Holder
Wafer
Polishing Pad
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38. 200 mm Wafer Thickness and Surface Roughness Changes
After Wafer Sawing
914 mm
76 mm
After Edge Rounding
914 mm
12.5 mm
After Lapping
814 mm
<2.5 mm
After Etch
750 mm
Virtually Defect Free
After CMP
725 mm
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39. Epitaxy Grow Definition Purposes Epitaxy Reactors Epitaxy Process
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40. Epitaxy: Definition Greek origin epi: upon taxy: orderly, arranged
Epitaxial layer is a single crystal layer on a single crystal substrate.
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41. Epitaxy: Purpose Barrier layer for bipolar transistor
Reduce collector resistance while keep high breakdown voltage.
Only available with epitaxy layer.
Improve device performance for CMOS and DRAM because much lower oxygen, carbon concentration than the wafer crystal.
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42. Epitaxy Application, Bipolar Transistor
Emitter
Base
Collector
Al•Cu•Si
SiO2 n + p n + p+ p+
n-Epi
Electron flow n +
Buried Layer
P-substrate
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43. Epitaxy Application: CMOS
Metal 1, Al•Cu W
BPSG n+ n+ p+ p+
STI
USG
P-Well
N-Well
P-type Epitaxy Silicon
P-Wafer
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44. Silicon Source Gases Silane SiH4 Dichlorosilane DCS SiH2Cl2
Trichlorosilane TCS SiHCl3
Tetrachlorosilane SiCl4
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45. Dopant Source Gases Diborane B2H6 Phosphine PH3 Arsine AsH3
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46. DCS Epitaxy Grow, Arsenic Doping
Heat (1100 C)
SiH2Cl2
Si HCl
DCS Epi Hydrochloride
AsH ® As /2 H2
Heat (1100 C)
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47. Schematic of DCS Epi Grow and Arsenic Doping Process
SiH2Cl2
AsH3 H2
HCl Si
AsH3 As H
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48. Epitaxial Silicon Growth Rate Trends
Temperature (°C)
1300
1200
1100
1000
900
800
700
1.0
0.5
SiH4
Mass transport limited
0.2
Growth Rate, micron/min
0.1
SiHCl3
0.05
Surface reaction limited
0.02
SiH2Cl2
0.01
0.7
0.8
0.9
1.0
1.1
1000/T(K)
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49. Barrel Reactor Radiation Heating Coils Wafers Hong Xiao, Ph. D.
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50. Vertical Reactor Wafers Reactants Heating Coils
Reactants and byproducts
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51. Horizontal Reactor Heating Coils Wafers Reactants
Reactants and byproducts
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52. Epitaxy Process, Batch System
Hydrogen purge, temperature ramp up
HCl clean
Epitaxial layer grow
Hydrogen purge, temperature cool down
Nitrogen purge
Open Chamber, wafer unloading, reloading
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53. Single Wafer Reactor Sealed chamber, hydrogen ambient
Capable for multiple chambers on a mainframe
Large wafer size (to 300 mm)
Better uniformity control
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54. Single Wafer Reactor Heat Radiation Heating Lamps Wafer Reactants
Reactants & byproducts
Susceptor
Quartz Lift Fingers
Quartz Window
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55. Epitaxy Process, Single Wafer System
Hydrogen purge, clean, temperature ramp up
Epitaxial layer grow
Hydrogen purge, heating power off
Wafer unloading, reloading
In-situ HCl clean,
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56. Why Hydrogen Purge Most systems use nitrogen as purge gas
Nitrogen is a very stable abundant
At > 1000 C, N2 can react with silicon
SiN on wafer surface affects epi deposition
H2 is used for epitaxy chamber purge
Clean wafer surface by hydrides formation
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57. Properties of Hydrogen
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58. Defects in Epitaxy Layer
Stacking Fault from Surface Nucleation
Stacking Fault form Substrate Stacking Fault
Dislocation
Impurity Particle
Hillock
Epi Layer
Substrate
After S.M. Zse’s VLSI Technology
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59. Future Trends Larger wafer size Single wafer epitaxial grow
Low temperature epitaxy
Ultra high vacuum (UHV, to 10-9 Torr)
Selective epitaxy
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60. Summary
Silicon is abundant, cheap and has strong, stable and easy grown oxide.
<100> and <111>
CZ and floating zone, CZ is more popular
Sawing, edging, lapping, etching and CMP
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61. Summary Epitaxy: single crystal on single crystal
Needed for bipolar and high performance CMOS, DRAM.
Silane, DCS, TCS as silicon precursors
B2H6 as P-type dopant
PH3 and AsH3 as N-type dopants
Batch and single wafer systems
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