1. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 1/25 Scalable bipolar transistor modelling with HICUM L0 S. Frégonèse, D. Berger *, T. Zimmer, C. Maneux, P. Y. Sulima, D. Céli * Laboratoire de Microélectronique IXL, FRANCE * ST Microelectronics, FRANCE

2. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 2/25 Outlines Introduction –Geometry Scaling –Modelling strategy –Why HICUM L0 ? HICUM L0 & L2 –Similarity between L2 and L0 –L0 equations Applications –Extraction –Impact of emitter via resistances –Impact of corner rounding –DC & AC measurement and model comparison Conclusion Perspectives

3. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 3/25 Introduction : Geometry scaling Transistor modelling with a function of emitter length and width as parameters –Circuit performances optimisation –Model many transistors with one parameter set Important parameter for scalable modelling of the internal transistor –Real length and width ( WE0 and LE0 ) Spacer have to be taken into account –Effective diffusion length under emitter window  C –Corner rounding Low size transistor –SIC window Internal & external base collector capacitances modelling Base Collector current E B C Mask r0r0 W E0 CC L E0

4. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 4/25 Introduction : Modelling Strategy Scaling level 1Scaling level 2Scaling level 3 Scaling rulesimplanted in a program outside the model (Tradica [ *] ) simulator preprocessor language inside the model Model cardOne for each transistor One for all transistors Optimisation of circuit performances with W & L Depends on its implementation in the design kit Easy Modification of scaling rules Easy with Master Toolkit XMOD * EasyEasy for research with Verilog A Link between ICCAP and Model Easy with Master Toolkit XMOD * DifficultVery Easy

5. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 5/25 Introduction : Why HICUM L0 ? A new model combining –Simplicity of Gummel Poon: Less computational effort (internal nodes number, L0 : 3,L2 : 5) Extraction is easier –Major features of HICUM Accurate charge description Self heating is taken into account Useful for: –Quick evaluation of the basic circuit functionality –For non critical transistor

6. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 6/25 HICUM L0 & L2 : Similarity between L0 and L2 Simplifications –Charge: Simplification of charge modelling in transfer current source DC and AC are uncorrelated. –Internal base node is suppressed External base resistance and internal base resistance are merged together External base-emitter capacitance and internal base-emitter capacitance are grouped together –Current source are merged: Peripheral and internal base-collector Peripheral and internal base-emitter –Others effects: Substrate network Parasistic transistor NQS effects Base-Emitter tunnelling current source

7. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 7/25 HICUM L0 & L2 : Similarity between L0 and L2 AC Charge formulation unchanged –Capacitance formulation –Transit time formulation At low & high current Critical current Internal base resistance: Temperature dependence & self heating Geometry dependent zero bias value is unchanged Bias variation function is simplified

8. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 8/25 HICUM L0 & L2 : L0 Equations -Transfer current source in HICUM L2 - Transfert current source in HICUM L0 - Low to medium current : -Low current: 2 scalable parameters 1 scalable parameter 1 constant parameter

9. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 9/25 HICUM L0 & L2 : L0 Equations - Charge increase for AC regime: Same equation as L2 - Charge increase for DC regime: AC et DC are uncorrelated f cs function parameter is extracted from R CI0 extraction ( from AC characteristics)

10. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 10/25 Applications : Extraction flow C BE, C BCi, C BCx, C CS  C and Collector current source (J cu, mcf) base-emitter & base- collector current source R E is extracted / R CX, R BX, R BI are calculated from layer resistivity Transit time @ low current  0I,  0P, T BVL, D T0H Critical current parameters R CI0U,  C, V CES, V PT, V LIM Transit time @ high current  EF0, G TE,  HCS, A LHC DC charge @ high current I QFHu,  FH

11. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 11/25 Applications : Extraction of Capacitance C BE =C BEpu P E0 +C BEsu A E0

12. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 12/25 Applications : Extraction of  C I C =J C (W E0 +2  C )(L E0 +2  C ) I C =0 if W E0 =-2  C Collector current versus emitter width for different V BE and V BC =0 V (measurement) E B C Mask r0r0 W E0 CC L E0

13. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 13/25 Applications: Extraction of Transit time Split into one internal part and into one peripheral part: –I c =I i +I p= J i A E0 +J p P E –Q total = Q 0i + Q 0P –Internal charge: Q 0i =  0i I i –Peripheral charge: Q 0P =  0P I P Equivalent transit time   =Q total /I c Scalable model [1] : Extracted  0 values versus emitter area for different emitter sizes. (1: 0.25*1.45 µm², 2: 0.25*3.05 µm², 3: 0.25*6.25 µm², 4: 0.25*12.65 µm², 5: 0.25*25.45 µm², 6: 0.65*12.65 µm², 7: 1.45*12.65 µm²) [1] Michael Schröeter et al. IEEE solid states circuits, vol.31, n°10, oct 1996

14. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 14/25 Applications : Extraction of Critical current parameter Critical current –Models the transit frequency fall- off –Link to Kirk effect Collector doping Internal collector resistance: Current spreading in the collector with a  C angle Scalable model [1] Extracted R CI0 values versus emitter area for different emitter sizes. (1: 0.25*1.45 µm², 2: 0.25*3.05 µm², 3: 0.25*6.25 µm², 4: 0.25*12.65 µm², 5: 0.25*25.45 µm², 6: 0.65*12.65 µm², 7: 1.45*12.65 µm²) with f cs [1] Michael Schröeter et al. IEEE solid states circuits, vol.31, n°10, oct 1996

15. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 15/25 Applications : Impact of vias on the emitter resistance Number of vias and emitter width is not proportional: –Simple model doesn’t work ( ) –Number of vias has to be calculated versus the width with layout rules: W E0 = 0.25 µm Nb_via = 1 W E0 = 0.65 µm Nb_via = 1 W E0 = 1.45 µm Nb_via = 2 Gummel plot@ V BC =0 V for 3emitter sizes (0.25, 0.65, 1.45*12.65 µm²) (model 1: taking into account via; model 2: without via)

16. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 16/25 Applications : Impact of Corner rounding r W E0 L E0 CC r CC [2] [2] Michael Schröeter et al. IEEE solid states circuits, vol.34, n°8, oct 1999 With r 0 (maximum value) =W E0 /2 Emitter sizes 1: 0.25*0.65 µm², 2: 0.25*1.45 µm², 3: 0.25*3.05 µm², 4: 0.25*6.25 µm², 5: 0.25*12.65 µm², 6: 0.25*25.45 µm²

17. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 17/25 Model is not physical But usefull for low size Applications : Impact of Corner rounding S1S1 r r r-w E /2 0 y LELE WEWE S Emitter sizes 1: 0.25*0.65 µm², 2: 0.25*1.45 µm², 3: 0.25*3.05 µm², 4: 0.25*6.25 µm², 5: 0.25*12.65 µm², 6: 0.25*25.45 µm²

18. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 18/25 Applications : DC measurement and model comparison BiCMOS 0.25 µm from STMicroelectronics 0.25*25.45 µm² 0.65*12.65 µm² 0.25*0.65 µm²

19. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 19/25 Applications : AC measurement and model comparison BiCMOS 0.25 µm from STMicroelectronics

20. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 20/25 Applications : AC measurement and model comparison Y parameters : Y=f(frequency,V CE =1.5 V) for 4 V BE (0.7 V, 0.8V, 0.9V, 1V) emitter size (0.25 * 12.65 µm²) BiCMOS 0.25 µm from STMicroelectronics

21. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 21/25 Applications : AC measurement and model comparison Y parameters : Y=f(frequency,V CE =1.5 V) for 4 V BE (0.7 V, 0.8V, 0.9V, 1V) emitter size (0.25 * 12.65 µm²) BiCMOS 0.25 µm from STMicroelectronics

22. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 22/25 Applications : AC measurement and model comparison Y parameters : Y=f(I C,V BC =0) for 3 widths (0.25 * 12.65 µm²,0.65 * 12.65 µm²,1.45 * 12.65 µm²) and @ 7 GHz BiCMOS 0.25 µm from STMicroelectronics

23. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 23/25 Applications : AC measurement and model comparison Y parameters : Y=f(I C,V BC =0) for 3 widths (0.25 * 12.65 µm²,0.65 * 12.65 µm²,1.45 * 12.65 µm²) and @ 7 GHz BiCMOS 0.25 µm from STMicroelectronics

24. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 24/25 Conclusion L0 can be enhanced (substrate network & Parasistic transistor) L0 has the Simplicity of Gummel Poon: Less computational effort Extraction is easier Electrical description is very good –Charge description But L2 is more precise for electrical description But L2 has convergence problems for : –Transient simulation with pulse for high slew rate Geometry Scaling with L0 can be realized This scalable model was used on a BiCMOS 0.25 µm STMicroelectronics technology. –DC and AC shows good agreements For different emitter size: –Width 0.25 µm -> 1.45 µm –Length 1.45 µm -> 25.45 µm

25. S. FREGONESE 19 juin 2004 HICUM WORKSHOP 2004 25/25 Perspectives Comparison of L0 model with measurement from –Very low size transistor –Faster transistor Enhancing model accuracy for specific physical effects (ex: High injection Barrier effects) SOI modelling